[PATCH] D47587: [RISCV] Codegen support for atomic operations on RV32I

[Alex Bradbury via Phabricator via llvm-commits]

asb added inline comments.


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Comment at: lib/Target/RISCV/RISCVInstrInfo.td:731
+// fence release -> fence rw, r
+def : Pat<(atomic_fence (i32 5), (imm)), (FENCE 3, 1)>;
+// fence acq_rel -> fence rw, rw (as fence.tso is not yet defined)
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jfb wrote:
> The table says this should be rw, w.
Fixed the comment, thanks.


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Comment at: lib/Target/RISCV/RISCVInstrInfo.td:732
+def : Pat<(atomic_fence (i32 5), (imm)), (FENCE 3, 1)>;
+// fence acq_rel -> fence rw, rw (as fence.tso is not yet defined)
+def : Pat<(atomic_fence (i32 6), (imm)), (FENCE 3, 3)>;
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jfb wrote:
> Can you define fence.tso first?
I'll clarify the comment. The memory model working group proposed that a new fence.tso instruction should be added to the base instruction set, but that proposal hasn't been accepted and even if it was we'd of course have to be very careful about emitting fence.tso for hardware that doesn't actually implement it.


https://reviews.llvm.org/D47587