[PATCH] D47730: [SelectionDAG]Reduce masked data movement chains and memory access widths pt2

[Javed Absar via Phabricator via llvm-commits]

javed.absar added inline comments.


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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:13003
+/// Replaces patterns such as:
+// store 2 ( or (load 1 from M), (shl (load 1 from M) 8 ) ) into M
+// by store 1 ( load 1 from M) into M+1
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I think the comment here can be improved.  e.g. 'load 1 from M' is confusing. You probably mean load i8 from memory?

Also, it looks like you are combing two points into one statement which may confuse readers. Better to simplify it.


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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:13009
+  if (OR.getOpcode() != ISD::OR)
+    llvm_unreachable("Assuming to be called with an OR operad.");
+  SDValue LoadSD = OR.getOperand(0);
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Would be better to return nullptr instead of 'llvm_unreachable' in case its not ISD::OR


Repository:
  rL LLVM

https://reviews.llvm.org/D47730