[PATCH] D47587: [RISCV] Codegen support for atomic operations on RV32I

[JF Bastien via Phabricator via llvm-commits]

jfb added inline comments.


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Comment at: lib/Target/RISCV/RISCVInstrInfo.td:731
+// fence release -> fence rw, r
+def : Pat<(atomic_fence (i32 5), (imm)), (FENCE 3, 1)>;
+// fence acq_rel -> fence rw, rw (as fence.tso is not yet defined)
----------------
The table says this should be rw, w.


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Comment at: lib/Target/RISCV/RISCVInstrInfo.td:732
+def : Pat<(atomic_fence (i32 5), (imm)), (FENCE 3, 1)>;
+// fence acq_rel -> fence rw, rw (as fence.tso is not yet defined)
+def : Pat<(atomic_fence (i32 6), (imm)), (FENCE 3, 3)>;
----------------
Can you define fence.tso first?


https://reviews.llvm.org/D47587