[PATCH] D47587: [RISCV] Codegen support for atomic operations on RV32I

[Alex Bradbury via Phabricator via llvm-commits]

asb created this revision.
asb added reviewers: jyknight, jfb, theraven, eli.friedman.
Herald added subscribers: mgrang, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, fedor.sergeev.

This patch adds lowering for atomic fences to the native RV32I fence instructions and relies on AtomicExpandPass to lower atomic loads/stores, atomic rmw, and cmpxchg to __atomic_* libcalls. Future patches add support for RV32A, providing atomics support without libcalls.

test/CodeGen/RISCV/atomic-* are modelled on the exhaustive test/CodeGen/PPC/atomics-regression.ll, and will prove more useful once RV32A codegen support is introduced. I'd welcome feedback on if I'm missing anything obvious. I believe that lowering fences but emitting __atomic libcalls otherwise seems to match the behaviour of other backends (e.g. Sparc) and seems correct, but I'd appreciate further opinions.

Fence mappings are taken from table A.6 in the [current draf](https://github.com/riscv/riscv-isa-manual/releases/download/draft-20180531-40cf935/riscv-spec.pdf)t of version 2.3 of the RISC-V Instruction Set Manual, which incorporates the memory model changes and definitions contributed by the RISC-V Memroy Consistency Model task group.


https://reviews.llvm.org/D47587

Files:
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVInstrInfo.td
  lib/Target/RISCV/RISCVTargetMachine.cpp
  test/CodeGen/RISCV/atomic-cmpxchg.ll
  test/CodeGen/RISCV/atomic-fence.ll
  test/CodeGen/RISCV/atomic-load-store.ll
  test/CodeGen/RISCV/atomic-rmw.ll

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