[PATCH] D46837: [MachineScheduler] Skip an implicit def of a super-reg added by regalloc in findDefIdx.

[Jonas Paulsson via Phabricator via llvm-commits]

jonpa added inline comments.


================
Comment at: lib/CodeGen/TargetSchedule.cpp:158
+/// with respect to each other.  We need to skip implicit def operands (added
+/// by regalloc) that are not part of the MCInstrDesc.
 static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx) {
----------------
materi wrote:
> "We need to skip..." looks strange to me.
> 
> I would prefer if an implicit operand means the same thing regardless of whether it's in the Tablegen file or not.
> 
> Maybe it's the adding of the implicit operand that you need to inhibit in your case?
I agree that this is all a bit strange to have to handle this way. This however not a special case, but as far as I know the long since behavior of the register allocator generally.

Since you can't write a scheduler description (where you have to list the def-operand latencies for each def-operand in the right order), based on what regalloc may or may not do, they can't be treated the same.

It seems weird that these regalloc operands end up in the middle of the operand list, but not sure if that's something we could fix now. This patch at least fixes the DAG operand latencies for now...




https://reviews.llvm.org/D46837