[PATCH] D45745: [AMDGPU] Enabled v2.16 literals for VOP3P

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

In https://reviews.llvm.org/D45745#1070665, @arsenm wrote:

> This looks simpler than I expect. Don' you need to change the operand classes of the packed instructions and check the 16-bit imm values?


Yes, that is simpler than I expected too. I do not really need to check immediates. These are all VOP3P, so only inline literals are allowed. Those always fit.



================
Comment at: llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp:157-158
 
   if (Fold.isImm()) {
+    if (MI->getDesc().TSFlags & SIInstrFlags::IsPacked) {
+      // Set op_sel_hi on this operand or bail out if op_sel is already set.
----------------
arsenm wrote:
> Is this just handling the case where both halves are the same, or is this supposed to handle the mixed case where either high or low is 0?
That is only for the case when high and low are equal. To get to this place it first must pass isOperandLegal check, which verifies both halfs are equal. We encode an inline constant and then use op_sel_hi to tell machine it must use low (and the only) part of the constant for high 16 bits too. Theoretically speaking we can also handle the case when hi 16 bit are zero, but that is not done now, it simply does not pass isInlinableLiteralV216() check. In most practical cases having zero in high part neglects the purpose of using packed instructions anyway.


Repository:
  rL LLVM

https://reviews.llvm.org/D45745