[llvm] r328960 - [X86] Correct the throughput for divide instructions in Sandy Bridge/Haswell/Broadwell/Skylake scheduler models.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 1 22:33:29 PDT 2018
Author: ctopper
Date: Sun Apr 1 22:33:28 2018
New Revision: 328960
URL: http://llvm.org/viewvc/llvm-project?rev=328960&view=rev
Log:
[X86] Correct the throughput for divide instructions in Sandy Bridge/Haswell/Broadwell/Skylake scheduler models.
Fixes most of PR36898. Still need to fix the 512-bit instructions, but Agner's tables don't have those.
Modified:
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
llvm/trunk/test/CodeGen/X86/avx-schedule.ll
llvm/trunk/test/CodeGen/X86/avx512-schedule.ll
llvm/trunk/test/CodeGen/X86/recip-fastmath.ll
llvm/trunk/test/CodeGen/X86/sse-schedule.ll
llvm/trunk/test/CodeGen/X86/sse2-schedule.ll
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=328960&r1=328959&r2=328960&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Sun Apr 1 22:33:28 2018
@@ -67,7 +67,9 @@ def BWPortAny : ProcResGroup<[BWPort0, B
}
// Integer division issued on port 0.
-def BWDivider : ProcResource<1>; // Integer division issued on port 0.
+def BWDivider : ProcResource<1>;
+// FP division and sqrt on port 0.
+def BWFPDivider : ProcResource<1>;
// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
// cycles after the memory operand.
@@ -2260,13 +2262,19 @@ def BWWriteResGroup121 : SchedWriteRes<[
}
def: InstRW<[BWWriteResGroup121], (instrs IMUL32m, MUL32m, MULX32rm)>;
-def BWWriteResGroup122 : SchedWriteRes<[BWPort0]> {
+def BWWriteResGroup122 : SchedWriteRes<[BWPort0,BWFPDivider]> {
let Latency = 11;
let NumMicroOps = 1;
- let ResourceCycles = [1];
+ let ResourceCycles = [1,5];
+}
+def: InstRW<[BWWriteResGroup122], (instregex "(V?)DIVPSrr")>;
+
+def BWWriteResGroup122_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
+ let Latency = 11;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,3]; // Really 2.5 cycle throughput
}
-def: InstRW<[BWWriteResGroup122], (instregex "(V?)DIVPSrr",
- "(V?)DIVSSrr")>;
+def: InstRW<[BWWriteResGroup122_1], (instregex "(V?)DIVSSrr")>;
def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> {
let Latency = 11;
@@ -2381,28 +2389,40 @@ def BWWriteResGroup136 : SchedWriteRes<[
}
def: InstRW<[BWWriteResGroup136], (instregex "(V?)MPSADBWrmi")>;
-def BWWriteResGroup137 : SchedWriteRes<[BWPort0]> {
+def BWWriteResGroup137 : SchedWriteRes<[BWPort0,BWFPDivider]> {
let Latency = 11;
let NumMicroOps = 1;
- let ResourceCycles = [1];
+ let ResourceCycles = [1,7];
+}
+def: InstRW<[BWWriteResGroup137], (instregex "(V?)SQRTPSr")>;
+
+def BWWriteResGroup137_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
+ let Latency = 11;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,4];
}
-def: InstRW<[BWWriteResGroup137], (instregex "(V?)SQRTPSr",
- "(V?)SQRTSSr")>;
+def: InstRW<[BWWriteResGroup137_1], (instregex "(V?)SQRTSSr")>;
def BWWriteResGroup138 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
let Latency = 13;
let NumMicroOps = 4;
- let ResourceCycles = [1,2,1];
+ let ResourceCycles = [1,2,1,7];
}
def: InstRW<[BWWriteResGroup138], (instregex "VMPSADBWYrmi")>;
-def BWWriteResGroup139 : SchedWriteRes<[BWPort0]> {
+def BWWriteResGroup139 : SchedWriteRes<[BWPort0,BWFPDivider]> {
let Latency = 14;
let NumMicroOps = 1;
- let ResourceCycles = [1];
+ let ResourceCycles = [1,8];
+}
+def: InstRW<[BWWriteResGroup139], (instregex "(V?)DIVPDrr")>;
+
+def BWWriteResGroup139_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
+ let Latency = 14;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,4];
}
-def: InstRW<[BWWriteResGroup139], (instregex "(V?)DIVPDrr",
- "(V?)DIVSDrr")>;
+def: InstRW<[BWWriteResGroup139_1], (instregex "(V?)DIVSDrr")>;
def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
let Latency = 14;
@@ -2463,10 +2483,10 @@ def BWWriteResGroup149 : SchedWriteRes<[
}
def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>;
-def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23]> {
+def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
let Latency = 16;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,5];
}
def: InstRW<[BWWriteResGroup150], (instregex "(V?)DIVPSrm",
"(V?)DIVSSrm")>;
@@ -2492,10 +2512,10 @@ def BWWriteResGroup154 : SchedWriteRes<[
}
def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>;
-def BWWriteResGroup155 : SchedWriteRes<[BWPort0,BWPort015]> {
+def BWWriteResGroup155 : SchedWriteRes<[BWPort0,BWPort015,BWFPDivider]> {
let Latency = 17;
let NumMicroOps = 3;
- let ResourceCycles = [2,1];
+ let ResourceCycles = [2,1,10];
}
def: InstRW<[BWWriteResGroup155], (instregex "VDIVPSYrr")>;
@@ -2507,10 +2527,10 @@ def BWWriteResGroup156 : SchedWriteRes<[
def: InstRW<[BWWriteResGroup156], (instregex "VRCPPSYm",
"VRSQRTPSYm")>;
-def BWWriteResGroup157 : SchedWriteRes<[BWPort0,BWPort23]> {
+def BWWriteResGroup157 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
let Latency = 16;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,7];
}
def: InstRW<[BWWriteResGroup157], (instregex "(V?)SQRTPSm",
"(V?)SQRTSSm")>;
@@ -2530,10 +2550,10 @@ def BWWriteResGroup160 : SchedWriteRes<[
}
def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>;
-def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23]> {
+def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
let Latency = 19;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,8];
}
def: InstRW<[BWWriteResGroup161], (instregex "(V?)DIVPDrm",
"(V?)DIVSDrm")>;
@@ -2570,13 +2590,19 @@ def: InstRW<[BWWriteResGroup167], (instr
"INSL",
"INSW")>;
-def BWWriteResGroup168 : SchedWriteRes<[BWPort0]> {
+def BWWriteResGroup168 : SchedWriteRes<[BWPort0,BWFPDivider]> {
let Latency = 16;
let NumMicroOps = 1;
- let ResourceCycles = [1];
+ let ResourceCycles = [1,14];
+}
+def: InstRW<[BWWriteResGroup168], (instregex "(V?)SQRTPDr")>;
+
+def BWWriteResGroup168_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
+ let Latency = 16;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,8];
}
-def: InstRW<[BWWriteResGroup168], (instregex "(V?)SQRTPDr",
- "(V?)SQRTSDr")>;
+def: InstRW<[BWWriteResGroup168_1], (instregex "(V?)SQRTSDr")>;
def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> {
let Latency = 21;
@@ -2586,10 +2612,10 @@ def BWWriteResGroup169 : SchedWriteRes<[
def: InstRW<[BWWriteResGroup169], (instregex "DIV_F32m",
"DIV_F64m")>;
-def BWWriteResGroup170 : SchedWriteRes<[BWPort0,BWPort015]> {
+def BWWriteResGroup170 : SchedWriteRes<[BWPort0,BWPort015,BWFPDivider]> {
let Latency = 21;
let NumMicroOps = 3;
- let ResourceCycles = [2,1];
+ let ResourceCycles = [2,1,14];
}
def: InstRW<[BWWriteResGroup170], (instregex "VSQRTPSYr")>;
@@ -2607,17 +2633,17 @@ def BWWriteResGroup172 : SchedWriteRes<[
}
def: InstRW<[BWWriteResGroup172], (instregex "POPF64")>;
-def BWWriteResGroup173 : SchedWriteRes<[BWPort0,BWPort015]> {
+def BWWriteResGroup173 : SchedWriteRes<[BWPort0,BWPort015,BWFPDivider]> {
let Latency = 23;
let NumMicroOps = 3;
- let ResourceCycles = [2,1];
+ let ResourceCycles = [2,1,16];
}
def: InstRW<[BWWriteResGroup173], (instregex "VDIVPDYrr")>;
-def BWWriteResGroup174 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
+def BWWriteResGroup174 : SchedWriteRes<[BWPort0,BWPort23,BWPort015,BWFPDivider]> {
let Latency = 23;
let NumMicroOps = 4;
- let ResourceCycles = [2,1,1];
+ let ResourceCycles = [2,1,1,10];
}
def: InstRW<[BWWriteResGroup174], (instregex "VDIVPSYrm")>;
@@ -2636,10 +2662,10 @@ def BWWriteResGroup177 : SchedWriteRes<[
def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI16m",
"DIV_FI32m")>;
-def BWWriteResGroup179 : SchedWriteRes<[BWPort0,BWPort23]> {
+def BWWriteResGroup179 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
let Latency = 21;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,14];
}
def: InstRW<[BWWriteResGroup179], (instregex "(V?)SQRTPDm",
"(V?)SQRTSDm")>;
@@ -2652,10 +2678,10 @@ def BWWriteResGroup180 : SchedWriteRes<[
def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F32m",
"DIVR_F64m")>;
-def BWWriteResGroup181 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
+def BWWriteResGroup181 : SchedWriteRes<[BWPort0,BWPort23,BWPort015,BWFPDivider]> {
let Latency = 27;
let NumMicroOps = 4;
- let ResourceCycles = [2,1,1];
+ let ResourceCycles = [2,1,1,14];
}
def: InstRW<[BWWriteResGroup181], (instregex "VSQRTPSYm")>;
@@ -2667,10 +2693,10 @@ def BWWriteResGroup182 : SchedWriteRes<[
def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI16m",
"DIVR_FI32m")>;
-def BWWriteResGroup183 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
+def BWWriteResGroup183 : SchedWriteRes<[BWPort0,BWPort23,BWPort015,BWFPDivider]> {
let Latency = 29;
let NumMicroOps = 4;
- let ResourceCycles = [2,1,1];
+ let ResourceCycles = [2,1,1,16];
}
def: InstRW<[BWWriteResGroup183], (instregex "VDIVPDYrm")>;
@@ -2745,10 +2771,10 @@ def BWWriteResGroup187 : SchedWriteRes<[
}
def: InstRW<[BWWriteResGroup187], (instregex "MMX_EMMS")>;
-def BWWriteResGroup189 : SchedWriteRes<[BWPort0,BWPort015]> {
- let Latency = 34;
+def BWWriteResGroup189 : SchedWriteRes<[BWPort0,BWPort015,BWFPDivider]> {
+ let Latency = 29;
let NumMicroOps = 3;
- let ResourceCycles = [2,1];
+ let ResourceCycles = [2,1,28];
}
def: InstRW<[BWWriteResGroup189], (instregex "VSQRTPDYr")>;
@@ -2782,10 +2808,10 @@ def BWWriteResGroup194 : SchedWriteRes<[
def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir",
"OUT(8|16|32)rr")>;
-def BWWriteResGroup195 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
- let Latency = 40;
+def BWWriteResGroup195 : SchedWriteRes<[BWPort0,BWPort23,BWPort015,BWFPDivider]> {
+ let Latency = 35;
let NumMicroOps = 4;
- let ResourceCycles = [2,1,1];
+ let ResourceCycles = [2,1,1,28];
}
def: InstRW<[BWWriteResGroup195], (instregex "VSQRTPDYm")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=328960&r1=328959&r2=328960&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Sun Apr 1 22:33:28 2018
@@ -69,6 +69,8 @@ def HWPortAny : ProcResGroup<[HWPort0, H
// Integer division issued on port 0.
def HWDivider : ProcResource<1>;
+// FP division and sqrt on port 0.
+def HWFPDivider : ProcResource<1>;
// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
// cycles after the memory operand.
@@ -2394,17 +2396,17 @@ def: InstRW<[HWWriteResGroup91], (instre
"(V?)RCPSSm",
"(V?)RSQRTSSm")>;
-def HWWriteResGroup91_1 : SchedWriteRes<[HWPort0,HWPort23]> {
+def HWWriteResGroup91_1 : SchedWriteRes<[HWPort0,HWPort23,HWFPDivider]> {
let Latency = 16;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,7];
}
def: InstRW<[HWWriteResGroup91_1], (instregex "(V?)SQRTSSm")>;
-def HWWriteResGroup91_4 : SchedWriteRes<[HWPort0,HWPort23]> {
+def HWWriteResGroup91_4 : SchedWriteRes<[HWPort0,HWPort23,HWFPDivider]> {
let Latency = 18;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,7];
}
def: InstRW<[HWWriteResGroup91_4], (instregex "(V?)DIVSSrm")>;
@@ -2695,10 +2697,10 @@ def HWWriteResGroup120 : SchedWriteRes<[
}
def: InstRW<[HWWriteResGroup120], (instregex "RCL(8|16|32|64)mCL")>;
-def HWWriteResGroup121 : SchedWriteRes<[HWPort0]> {
+def HWWriteResGroup121 : SchedWriteRes<[HWPort0,HWFPDivider]> {
let Latency = 13;
let NumMicroOps = 1;
- let ResourceCycles = [1];
+ let ResourceCycles = [1,7];
}
def: InstRW<[HWWriteResGroup121], (instregex "(V?)DIVPSrr",
"(V?)DIVSSrr")>;
@@ -2748,18 +2750,18 @@ def HWWriteResGroup132 : SchedWriteRes<[
}
def: InstRW<[HWWriteResGroup132], (instregex "CMPXCHG8B")>;
-def HWWriteResGroup133 : SchedWriteRes<[HWPort0]> {
+def HWWriteResGroup133 : SchedWriteRes<[HWPort0,HWFPDivider]> {
let Latency = 11;
let NumMicroOps = 1;
- let ResourceCycles = [1];
+ let ResourceCycles = [1,7];
}
def: InstRW<[HWWriteResGroup133], (instregex "(V?)SQRTPSr",
"(V?)SQRTSSr")>;
-def HWWriteResGroup134 : SchedWriteRes<[HWPort0,HWPort23]> {
+def HWWriteResGroup134 : SchedWriteRes<[HWPort0,HWPort23,HWFPDivider]> {
let Latency = 19;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,7];
}
def: InstRW<[HWWriteResGroup134], (instregex "(V?)DIVPSrm")>;
@@ -2770,10 +2772,10 @@ def HWWriteResGroup135 : SchedWriteRes<[
}
def: InstRW<[HWWriteResGroup135], (instregex "RCR(8|16|32|64)mCL")>;
-def HWWriteResGroup138 : SchedWriteRes<[HWPort0,HWPort23]> {
+def HWWriteResGroup138 : SchedWriteRes<[HWPort0,HWPort23,HWFPDivider]> {
let Latency = 17;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,7];
}
def: InstRW<[HWWriteResGroup138], (instregex "(V?)SQRTPSm")>;
@@ -2864,9 +2866,15 @@ def HWWriteResGroup154 : SchedWriteRes<[
}
def: InstRW<[HWWriteResGroup154], (instregex "DIV_FPrST0",
"DIV_FST0r",
- "DIV_FrST0",
- "(V?)DIVPDrr",
- "(V?)DIVSDrr")>;
+ "DIV_FrST0")>;
+
+def HWWriteResGroup154_1 : SchedWriteRes<[HWPort0,HWFPDivider]> {
+ let Latency = 20;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,14];
+}
+def: InstRW<[HWWriteResGroup154_1], (instregex "(V?)DIVPDrr",
+ "(V?)DIVSDrr")>;
def HWWriteResGroup155 : SchedWriteRes<[HWPort0,HWPort23]> {
let Latency = 27;
@@ -2876,31 +2884,31 @@ def HWWriteResGroup155 : SchedWriteRes<[
def: InstRW<[HWWriteResGroup155], (instregex "DIVR_F32m",
"DIVR_F64m")>;
-def HWWriteResGroup155_1 : SchedWriteRes<[HWPort0,HWPort23]> {
+def HWWriteResGroup155_1 : SchedWriteRes<[HWPort0,HWPort23,HWFPDivider]> {
let Latency = 26;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,14];
}
def: InstRW<[HWWriteResGroup155_1], (instregex "(V?)DIVPDrm")>;
-def HWWriteResGroup155_2 : SchedWriteRes<[HWPort0,HWPort23]> {
+def HWWriteResGroup155_2 : SchedWriteRes<[HWPort0,HWPort23,HWFPDivider]> {
let Latency = 21;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,14];
}
def: InstRW<[HWWriteResGroup155_2], (instregex "(V?)SQRTSDm")>;
-def HWWriteResGroup155_3 : SchedWriteRes<[HWPort0,HWPort23]> {
+def HWWriteResGroup155_3 : SchedWriteRes<[HWPort0,HWPort23,HWFPDivider]> {
let Latency = 22;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,14];
}
def: InstRW<[HWWriteResGroup155_3], (instregex "(V?)SQRTPDm")>;
-def HWWriteResGroup155_4 : SchedWriteRes<[HWPort0,HWPort23]> {
+def HWWriteResGroup155_4 : SchedWriteRes<[HWPort0,HWPort23,HWFPDivider]> {
let Latency = 25;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,14];
}
def: InstRW<[HWWriteResGroup155_4], (instregex "(V?)DIVSDrm")>;
@@ -2911,26 +2919,26 @@ def HWWriteResGroup156 : SchedWriteRes<[
}
def: InstRW<[HWWriteResGroup156], (instregex "MWAITrr")>;
-def HWWriteResGroup157 : SchedWriteRes<[HWPort0]> {
+def HWWriteResGroup157 : SchedWriteRes<[HWPort0,HWFPDivider]> {
let Latency = 16;
let NumMicroOps = 1;
- let ResourceCycles = [1];
+ let ResourceCycles = [1,14];
}
def: InstRW<[HWWriteResGroup157], (instregex "(V?)SQRTPDr",
"(V?)SQRTSDr")>;
-def HWWriteResGroup159 : SchedWriteRes<[HWPort0,HWPort015]> {
+def HWWriteResGroup159 : SchedWriteRes<[HWPort0,HWPort15,HWFPDivider]> {
let Latency = 21;
let NumMicroOps = 3;
- let ResourceCycles = [2,1];
+ let ResourceCycles = [2,1,14];
}
def: InstRW<[HWWriteResGroup159], (instregex "VDIVPSYrr",
"VSQRTPSYr")>;
-def HWWriteResGroup160 : SchedWriteRes<[HWPort0,HWPort23,HWPort015]> {
+def HWWriteResGroup160 : SchedWriteRes<[HWPort0,HWPort23,HWPort15,HWFPDivider]> {
let Latency = 28;
let NumMicroOps = 4;
- let ResourceCycles = [2,1,1];
+ let ResourceCycles = [2,1,1,14];
}
def: InstRW<[HWWriteResGroup160], (instregex "VDIVPSYrm",
"VSQRTPSYm")>;
@@ -3005,18 +3013,18 @@ def HWWriteResGroup172 : SchedWriteRes<[
}
def: InstRW<[HWWriteResGroup172], (instregex "MMX_EMMS")>;
-def HWWriteResGroup173 : SchedWriteRes<[HWPort0,HWPort015]> {
+def HWWriteResGroup173 : SchedWriteRes<[HWPort0,HWPort15,HWFPDivider]> {
let Latency = 35;
let NumMicroOps = 3;
- let ResourceCycles = [2,1];
+ let ResourceCycles = [2,1,28];
}
def: InstRW<[HWWriteResGroup173], (instregex "VDIVPDYrr",
"VSQRTPDYr")>;
-def HWWriteResGroup174 : SchedWriteRes<[HWPort0,HWPort23,HWPort015]> {
+def HWWriteResGroup174 : SchedWriteRes<[HWPort0,HWPort23,HWPort15,HWFPDivider]> {
let Latency = 42;
let NumMicroOps = 4;
- let ResourceCycles = [2,1,1];
+ let ResourceCycles = [2,1,1,28];
}
def: InstRW<[HWWriteResGroup174], (instregex "VDIVPDYrm",
"VSQRTPDYm")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=328960&r1=328959&r2=328960&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Sun Apr 1 22:33:28 2018
@@ -60,6 +60,8 @@ def SBPortAny : ProcResGroup<[SBPort0, S
// Integer division issued on port 0.
def SBDivider : ProcResource<1>;
+// FP division and sqrt on port 0.
+def SBFPDivider : ProcResource<1>;
// Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4
// cycles after the memory operand.
@@ -1931,10 +1933,10 @@ def: InstRW<[SBWriteResGroup114], (instr
"SUB_FI16m",
"SUB_FI32m")>;
-def SBWriteResGroup116 : SchedWriteRes<[SBPort0]> {
+def SBWriteResGroup116 : SchedWriteRes<[SBPort0,SBFPDivider]> {
let Latency = 14;
let NumMicroOps = 1;
- let ResourceCycles = [1];
+ let ResourceCycles = [1,14];
}
def: InstRW<[SBWriteResGroup116], (instregex "(V?)SQRTSSr",
"(V?)DIVPSrr",
@@ -1964,36 +1966,36 @@ def SBWriteResGroup120 : SchedWriteRes<[
}
def: InstRW<[SBWriteResGroup120], (instregex "(V?)DPPDrmi")>;
-def SBWriteResGroup123 : SchedWriteRes<[SBPort0,SBPort23]> {
+def SBWriteResGroup123 : SchedWriteRes<[SBPort0,SBPort23,SBFPDivider]> {
let Latency = 20;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,14];
}
def: InstRW<[SBWriteResGroup123], (instregex "(V?)SQRTSSm",
"(V?)DIVPSrm",
"(V?)DIVSSrm",
"(V?)SQRTPSm")>;
-def SBWriteResGroup124 : SchedWriteRes<[SBPort0]> {
+def SBWriteResGroup124 : SchedWriteRes<[SBPort0,SBFPDivider]> {
let Latency = 21;
let NumMicroOps = 1;
- let ResourceCycles = [1];
+ let ResourceCycles = [1,21];
}
def: InstRW<[SBWriteResGroup124], (instregex "(V?)SQRTPDr",
"(V?)SQRTSDr")>;
-def SBWriteResGroup125 : SchedWriteRes<[SBPort0,SBPort23]> {
+def SBWriteResGroup125 : SchedWriteRes<[SBPort0,SBPort23,SBFPDivider]> {
let Latency = 27;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,21];
}
def: InstRW<[SBWriteResGroup125], (instregex "(V?)SQRTPDm",
"(V?)SQRTSDm")>;
-def SBWriteResGroup126 : SchedWriteRes<[SBPort0]> {
+def SBWriteResGroup126 : SchedWriteRes<[SBPort0,SBFPDivider]> {
let Latency = 22;
let NumMicroOps = 1;
- let ResourceCycles = [1];
+ let ResourceCycles = [1,22];
}
def: InstRW<[SBWriteResGroup126], (instregex "(V?)DIVPDrr",
"(V?)DIVSDrr")>;
@@ -2010,18 +2012,18 @@ def: InstRW<[SBWriteResGroup127], (instr
"DIV_FST0r",
"DIV_FrST0")>;
-def SBWriteResGroup128 : SchedWriteRes<[SBPort0,SBPort23]> {
+def SBWriteResGroup128 : SchedWriteRes<[SBPort0,SBPort23,SBFPDivider]> {
let Latency = 28;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,22];
}
def: InstRW<[SBWriteResGroup128], (instregex "(V?)DIVPDrm",
"(V?)DIVSDrm")>;
-def SBWriteResGroup129 : SchedWriteRes<[SBPort0,SBPort05]> {
+def SBWriteResGroup129 : SchedWriteRes<[SBPort0,SBPort05,SBFPDivider]> {
let Latency = 29;
let NumMicroOps = 3;
- let ResourceCycles = [2,1];
+ let ResourceCycles = [2,1,28];
}
def: InstRW<[SBWriteResGroup129], (instregex "VDIVPSYrr",
"VSQRTPSYr")>;
@@ -2046,26 +2048,26 @@ def: InstRW<[SBWriteResGroup131], (instr
"DIV_FI16m",
"DIV_FI32m")>;
-def SBWriteResGroup132 : SchedWriteRes<[SBPort0,SBPort23,SBPort05]> {
+def SBWriteResGroup132 : SchedWriteRes<[SBPort0,SBPort23,SBPort05,SBFPDivider]> {
let Latency = 36;
let NumMicroOps = 4;
- let ResourceCycles = [2,1,1];
+ let ResourceCycles = [2,1,1,28];
}
def: InstRW<[SBWriteResGroup132], (instregex "VDIVPSYrm",
"VSQRTPSYm")>;
-def SBWriteResGroup133 : SchedWriteRes<[SBPort0,SBPort05]> {
+def SBWriteResGroup133 : SchedWriteRes<[SBPort0,SBPort05,SBFPDivider]> {
let Latency = 45;
let NumMicroOps = 3;
- let ResourceCycles = [2,1];
+ let ResourceCycles = [2,1,44];
}
def: InstRW<[SBWriteResGroup133], (instregex "VDIVPDYrr",
"VSQRTPDYr")>;
-def SBWriteResGroup134 : SchedWriteRes<[SBPort0,SBPort23,SBPort05]> {
+def SBWriteResGroup134 : SchedWriteRes<[SBPort0,SBPort23,SBPort05,SBFPDivider]> {
let Latency = 52;
let NumMicroOps = 4;
- let ResourceCycles = [2,1,1];
+ let ResourceCycles = [2,1,1,44];
}
def: InstRW<[SBWriteResGroup134], (instregex "VDIVPDYrm",
"VSQRTPDYm")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=328960&r1=328959&r2=328960&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Sun Apr 1 22:33:28 2018
@@ -62,6 +62,8 @@ def SKLPort056 : ProcResGroup<[SKLPort0,
def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>;
def SKLDivider : ProcResource<1>; // Integer division issued on port 0.
+// FP division and sqrt on port 0.
+def SKLFPDivider : ProcResource<1>;
// 60 Entry Unified Scheduler
def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4,
@@ -2343,14 +2345,21 @@ def SKLWriteResGroup144 : SchedWriteRes<
}
def: InstRW<[SKLWriteResGroup144], (instregex "MMX_EMMS")>;
-def SKLWriteResGroup145 : SchedWriteRes<[SKLPort0]> {
+def SKLWriteResGroup145 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
let Latency = 11;
let NumMicroOps = 1;
- let ResourceCycles = [1];
+ let ResourceCycles = [1,3];
}
-def: InstRW<[SKLWriteResGroup145], (instregex "(V?)DIVPS(Y?)rr",
+def: InstRW<[SKLWriteResGroup145], (instregex "(V?)DIVPSrr",
"(V?)DIVSSrr")>;
+def SKLWriteResGroup145_1 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
+ let Latency = 11;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,5];
+}
+def: InstRW<[SKLWriteResGroup145_1], (instregex "VDIVPSYrr")>;
+
def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> {
let Latency = 11;
let NumMicroOps = 2;
@@ -2468,14 +2477,21 @@ def SKLWriteResGroup156 : SchedWriteRes<
}
def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>;
-def SKLWriteResGroup157 : SchedWriteRes<[SKLPort0]> {
+def SKLWriteResGroup157 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
let Latency = 12;
let NumMicroOps = 1;
- let ResourceCycles = [1];
+ let ResourceCycles = [1,3];
}
-def: InstRW<[SKLWriteResGroup157], (instregex "(V?)SQRTPS(Y?)r",
+def: InstRW<[SKLWriteResGroup157], (instregex "(V?)SQRTPSr",
"(V?)SQRTSSr")>;
+def SKLWriteResGroup158 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
+ let Latency = 12;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,6];
+}
+def: InstRW<[SKLWriteResGroup158], (instregex "VSQRTPSYr")>;
+
def SKLWriteResGroup159 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
let Latency = 12;
let NumMicroOps = 4;
@@ -2529,14 +2545,21 @@ def: InstRW<[SKLWriteResGroup165], (inst
"VHSUBPDYrm",
"VHSUBPSYrm")>;
-def SKLWriteResGroup166 : SchedWriteRes<[SKLPort0]> {
+def SKLWriteResGroup166 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
let Latency = 14;
let NumMicroOps = 1;
- let ResourceCycles = [1];
+ let ResourceCycles = [1,3];
}
-def: InstRW<[SKLWriteResGroup166], (instregex "(V?)DIVPD(Y?)rr",
+def: InstRW<[SKLWriteResGroup166], (instregex "(V?)DIVPDrr",
"(V?)DIVSDrr")>;
+def SKLWriteResGroup166_1 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
+ let Latency = 14;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,5];
+}
+def: InstRW<[SKLWriteResGroup166_1], (instregex "VDIVPDYrr")>;
+
def SKLWriteResGroup168 : SchedWriteRes<[SKLPort23,SKLPort01]> {
let Latency = 14;
let NumMicroOps = 3;
@@ -2600,10 +2623,10 @@ def SKLWriteResGroup174 : SchedWriteRes<
}
def: InstRW<[SKLWriteResGroup174], (instregex "RCL(8|16|32|64)mCL")>;
-def SKLWriteResGroup175 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+def SKLWriteResGroup175 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
let Latency = 16;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,3];
}
def: InstRW<[SKLWriteResGroup175], (instregex "(V?)DIVSSrm")>;
@@ -2621,13 +2644,19 @@ def SKLWriteResGroup178 : SchedWriteRes<
}
def: InstRW<[SKLWriteResGroup178], (instregex "VZEROALL")>;
-def SKLWriteResGroup179 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+def SKLWriteResGroup179 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
let Latency = 17;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,5];
}
-def: InstRW<[SKLWriteResGroup179], (instregex "(V?)DIVPSrm",
- "(V?)SQRTSSm")>;
+def: InstRW<[SKLWriteResGroup179], (instregex "(V?)DIVPSrm")>;
+
+def SKLWriteResGroup179_1 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
+ let Latency = 17;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1,3];
+}
+def: InstRW<[SKLWriteResGroup179_1], (instregex "(V?)SQRTSSm")>;
def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
let Latency = 17;
@@ -2636,21 +2665,34 @@ def SKLWriteResGroup180 : SchedWriteRes<
}
def: InstRW<[SKLWriteResGroup180], (instregex "XCH_F")>;
-def SKLWriteResGroup181 : SchedWriteRes<[SKLPort0]> {
+def SKLWriteResGroup181 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
let Latency = 18;
let NumMicroOps = 1;
- let ResourceCycles = [1];
+ let ResourceCycles = [1,6];
}
-def: InstRW<[SKLWriteResGroup181], (instregex "(V?)SQRTPD(Y?)r",
+def: InstRW<[SKLWriteResGroup181], (instregex "(V?)SQRTPDr",
"(V?)SQRTSDr")>;
-def SKLWriteResGroup182 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+def SKLWriteResGroup181_1 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
+ let Latency = 18;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,12];
+}
+def: InstRW<[SKLWriteResGroup181_1], (instregex "VSQRTPDYr")>;
+
+def SKLWriteResGroup182 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
let Latency = 18;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,5];
+}
+def: InstRW<[SKLWriteResGroup182], (instregex "VDIVPSYrm")>;
+
+def SKLWriteResGroup183 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
+ let Latency = 18;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1,3];
}
-def: InstRW<[SKLWriteResGroup182], (instregex "VDIVPSYrm",
- "(V?)SQRTPSm")>;
+def: InstRW<[SKLWriteResGroup183], (instregex "(V?)SQRTPSm")>;
def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
let Latency = 18;
@@ -2666,13 +2708,19 @@ def SKLWriteResGroup185 : SchedWriteRes<
}
def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>;
-def SKLWriteResGroup186 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+def SKLWriteResGroup186 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
let Latency = 19;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,4];
+}
+def: InstRW<[SKLWriteResGroup186], (instregex "(V?)DIVSDrm")>;
+
+def SKLWriteResGroup186_1 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
+ let Latency = 19;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1,6];
}
-def: InstRW<[SKLWriteResGroup186], (instregex "(V?)DIVSDrm",
- "VSQRTPSYm")>;
+def: InstRW<[SKLWriteResGroup186_1], (instregex "VSQRTPSYm")>;
def SKLWriteResGroup187 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
let Latency = 19;
@@ -2690,10 +2738,10 @@ def: InstRW<[SKLWriteResGroup189], (inst
"DIV_FST0r",
"DIV_FrST0")>;
-def SKLWriteResGroup190 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+def SKLWriteResGroup190 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
let Latency = 20;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,4];
}
def: InstRW<[SKLWriteResGroup190], (instregex "(V?)DIVPDrm")>;
@@ -2720,10 +2768,10 @@ def SKLWriteResGroup193 : SchedWriteRes<
}
def: InstRW<[SKLWriteResGroup193], (instregex "MWAITrr")>;
-def SKLWriteResGroup195 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+def SKLWriteResGroup195 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
let Latency = 21;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,8];
}
def: InstRW<[SKLWriteResGroup195], (instregex "VDIVPDYrm")>;
@@ -2763,10 +2811,10 @@ def: InstRW<[SKLWriteResGroup196_2], (in
VPGATHERQQYrm,
VGATHERDPDYrm)>;
-def SKLWriteResGroup197 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+def SKLWriteResGroup197 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
let Latency = 23;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,6];
}
def: InstRW<[SKLWriteResGroup197], (instregex "(V?)SQRTSDm")>;
@@ -2777,17 +2825,17 @@ def SKLWriteResGroup198 : SchedWriteRes<
}
def: InstRW<[SKLWriteResGroup198], (instregex "CMPXCHG16B")>;
-def SKLWriteResGroup199 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+def SKLWriteResGroup199 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
let Latency = 24;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,6];
}
def: InstRW<[SKLWriteResGroup199], (instregex "(V?)SQRTPDm")>;
-def SKLWriteResGroup201 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+def SKLWriteResGroup201 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
let Latency = 25;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,12];
}
def: InstRW<[SKLWriteResGroup201], (instregex "VSQRTPDYm")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=328960&r1=328959&r2=328960&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Sun Apr 1 22:33:28 2018
@@ -62,6 +62,8 @@ def SKXPort056 : ProcResGroup<[SKXPort0,
def SKXPort0156: ProcResGroup<[SKXPort0, SKXPort1, SKXPort5, SKXPort6]>;
def SKXDivider : ProcResource<1>; // Integer division issued on port 0.
+// FP division and sqrt on port 0.
+def SKXFPDivider : ProcResource<1>;
// 60 Entry Unified Scheduler
def SKXPortAny : ProcResGroup<[SKXPort0, SKXPort1, SKXPort2, SKXPort3, SKXPort4,
@@ -5044,19 +5046,20 @@ def SKXWriteResGroup158 : SchedWriteRes<
}
def: InstRW<[SKXWriteResGroup158], (instregex "MMX_EMMS")>;
-def SKXWriteResGroup159 : SchedWriteRes<[SKXPort0]> {
+def SKXWriteResGroup159 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
let Latency = 11;
let NumMicroOps = 1;
- let ResourceCycles = [1];
+ let ResourceCycles = [1,3];
+}
+def: InstRW<[SKXWriteResGroup159], (instregex "(V?)DIVPS(Z128)?rr",
+ "(V?)DIVSS(Z?)rr")>;
+
+def SKXWriteResGroup159_1 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
+ let Latency = 11;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,5];
}
-def: InstRW<[SKXWriteResGroup159], (instregex "DIVPSrr",
- "DIVSSrr",
- "VDIVPSYrr",
- "VDIVPSZ128rr(b?)",
- "VDIVPSZ256rr(b?)",
- "VDIVPSrr",
- "VDIVSSZrr",
- "VDIVSSrr")>;
+def: InstRW<[SKXWriteResGroup159_1], (instregex "VDIVPS(Y|Z256)rr")>;
def SKXWriteResGroup160 : SchedWriteRes<[SKXPort0,SKXPort23]> {
let Latency = 11;
@@ -5325,19 +5328,20 @@ def SKXWriteResGroup171 : SchedWriteRes<
}
def: InstRW<[SKXWriteResGroup171], (instrs LOOPE, LOOPNE)>;
-def SKXWriteResGroup172 : SchedWriteRes<[SKXPort0]> {
+def SKXWriteResGroup172 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
let Latency = 12;
let NumMicroOps = 1;
- let ResourceCycles = [1];
+ let ResourceCycles = [1,3];
+}
+def: InstRW<[SKXWriteResGroup172], (instregex "(V?)SQRTPS(Z128)?r",
+ "(V?)SQRTSS(Z?)r")>;
+
+def SKXWriteResGroup173 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
+ let Latency = 12;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,6];
}
-def: InstRW<[SKXWriteResGroup172], (instregex "SQRTPSr",
- "SQRTSSr",
- "VSQRTPSYr",
- "VSQRTPSZ128r",
- "VSQRTPSZ256r",
- "VSQRTPSr",
- "VSQRTSSZr",
- "VSQRTSSr")>;
+def: InstRW<[SKXWriteResGroup173], (instregex "VSQRTPS(Y|Z256)r")>;
def SKXWriteResGroup174 : SchedWriteRes<[SKXPort015]> {
let Latency = 12;
@@ -5434,19 +5438,20 @@ def: InstRW<[SKXWriteResGroup183], (inst
"VPERMI2W128rm(b?)",
"VPERMT2W128rm(b?)")>;
-def SKXWriteResGroup184 : SchedWriteRes<[SKXPort0]> {
+def SKXWriteResGroup184 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
let Latency = 14;
let NumMicroOps = 1;
- let ResourceCycles = [1];
+ let ResourceCycles = [1,3];
+}
+def: InstRW<[SKXWriteResGroup184], (instregex "(V?)DIVPDrr",
+ "(V?)DIVSD(Z?)rr")>;
+
+def SKXWriteResGroup184_1 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
+ let Latency = 14;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,5];
}
-def: InstRW<[SKXWriteResGroup184], (instregex "DIVPDrr",
- "DIVSDrr",
- "VDIVPDYrr",
- "VDIVPDZ128rr(b?)",
- "VDIVPDZ256rr(b?)",
- "VDIVPDrr",
- "VDIVSDZrr",
- "VDIVSDrr")>;
+def: InstRW<[SKXWriteResGroup184_1], (instregex "VDIVPD(Y|Z256)rr")>;
def SKXWriteResGroup186 : SchedWriteRes<[SKXPort23,SKXPort015]> {
let Latency = 14;
@@ -5564,12 +5569,12 @@ def SKXWriteResGroup195 : SchedWriteRes<
}
def: InstRW<[SKXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>;
-def SKXWriteResGroup196 : SchedWriteRes<[SKXPort0,SKXPort23]> {
+def SKXWriteResGroup196 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
let Latency = 16;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,3];
}
-def: InstRW<[SKXWriteResGroup196], (instregex "(V?)DIVSSrm")>;
+def: InstRW<[SKXWriteResGroup196], (instregex "(V?)DIVSS(Z?)rm")>;
def SKXWriteResGroup198 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> {
let Latency = 16;
@@ -5595,18 +5600,19 @@ def SKXWriteResGroup200 : SchedWriteRes<
}
def: InstRW<[SKXWriteResGroup200], (instregex "VZEROALL")>;
-def SKXWriteResGroup201 : SchedWriteRes<[SKXPort0,SKXPort23]> {
+def SKXWriteResGroup201 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
let Latency = 17;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,5];
}
-def: InstRW<[SKXWriteResGroup201], (instregex "DIVPSrm",
- "SQRTSSm",
- "VDIVPSZ128rm(b?)",
- "VDIVPSrm",
- "VDIVSSZrm",
- "VSQRTSSm",
- "VSQRTSSZm")>;
+def: InstRW<[SKXWriteResGroup201], (instregex "(V?)DIVPS(Z128)?rm")>;
+
+def SKXWriteResGroup201_1 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
+ let Latency = 17;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1,3];
+}
+def: InstRW<[SKXWriteResGroup201_1], (instregex "(V?)SQRTSS(Z?)m")>;
def SKXWriteResGroup202 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156]> {
let Latency = 17;
@@ -5615,30 +5621,34 @@ def SKXWriteResGroup202 : SchedWriteRes<
}
def: InstRW<[SKXWriteResGroup202], (instregex "XCH_F")>;
-def SKXWriteResGroup203 : SchedWriteRes<[SKXPort0]> {
+def SKXWriteResGroup203 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
let Latency = 18;
let NumMicroOps = 1;
- let ResourceCycles = [1];
+ let ResourceCycles = [1,6];
+}
+def: InstRW<[SKXWriteResGroup203], (instregex "(V?)SQRTPD(Z128)?r",
+ "(V?)SQRTSD(Z?)r")>;
+
+def SKXWriteResGroup203_1 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
+ let Latency = 18;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,12];
}
-def: InstRW<[SKXWriteResGroup203], (instregex "SQRTPDr",
- "SQRTSDr",
- "VSQRTPDYr",
- "VSQRTPDZ128r(b?)",
- "VSQRTPDZ256r(b?)",
- "VSQRTPDr",
- "VSQRTSDZr",
- "VSQRTSDr")>;
+def: InstRW<[SKXWriteResGroup203_1], (instregex "VSQRTPD(Y|Z256)r")>;
-def SKXWriteResGroup204 : SchedWriteRes<[SKXPort0,SKXPort23]> {
+def SKXWriteResGroup204 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
let Latency = 18;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,5];
+}
+def: InstRW<[SKXWriteResGroup204], (instregex "VDIVPS(Y|Z256)rm")>;
+
+def SKXWriteResGroup204_1 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
+ let Latency = 18;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1,3];
}
-def: InstRW<[SKXWriteResGroup204], (instregex "SQRTPSm",
- "VDIVPSYrm",
- "VDIVPSZ256rm(b?)",
- "VSQRTPSZ128m(b?)",
- "VSQRTPSm")>;
+def: InstRW<[SKXWriteResGroup204_1], (instregex "(V?)SQRTPS(Z128)?m")>;
def SKXWriteResGroup205 : SchedWriteRes<[SKXPort23,SKXPort015]> {
let Latency = 18;
@@ -5661,16 +5671,21 @@ def SKXWriteResGroup208 : SchedWriteRes<
}
def: InstRW<[SKXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>;
-def SKXWriteResGroup209 : SchedWriteRes<[SKXPort0,SKXPort23]> {
+def SKXWriteResGroup209 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
let Latency = 19;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,4];
+}
+def: InstRW<[SKXWriteResGroup209], (instregex "(V?)DIVSD(Z?)rm")>;
+
+def SKXWriteResGroup209_1 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
+ let Latency = 19;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1,6];
}
-def: InstRW<[SKXWriteResGroup209], (instregex "DIVSDrm",
- "VDIVSDrm",
- "VSQRTPSYm",
- "VSQRTPSZ256m(b?)")>;
+def: InstRW<[SKXWriteResGroup209_1], (instregex "VSQRTPS(Y|Z256)m")>;
+//FIXME
def SKXWriteResGroup210 : SchedWriteRes<[SKXPort0,SKXPort015]> {
let Latency = 19;
let NumMicroOps = 3;
@@ -5710,14 +5725,12 @@ def: InstRW<[SKXWriteResGroup215], (inst
"DIV_FST0r",
"DIV_FrST0")>;
-def SKXWriteResGroup216 : SchedWriteRes<[SKXPort0,SKXPort23]> {
+def SKXWriteResGroup216 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
let Latency = 20;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,4];
}
-def: InstRW<[SKXWriteResGroup216], (instregex "(V?)DIVPDrm",
- "VDIVPDZ128rm(b?)",
- "VDIVSDZrm")>;
+def: InstRW<[SKXWriteResGroup216], (instregex "(V?)DIVPD(Z128)?rm")>;
def SKXWriteResGroup217 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
let Latency = 20;
@@ -5752,13 +5765,12 @@ def SKXWriteResGroup220 : SchedWriteRes<
}
def: InstRW<[SKXWriteResGroup220], (instregex "MWAITrr")>;
-def SKXWriteResGroup222 : SchedWriteRes<[SKXPort0,SKXPort23]> {
+def SKXWriteResGroup222 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
let Latency = 21;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,8];
}
-def: InstRW<[SKXWriteResGroup222], (instregex "VDIVPDYrm",
- "VDIVPDZ256rm(b?)")>;
+def: InstRW<[SKXWriteResGroup222], (instregex "VDIVPD(Y|Z256)rm")>;
def SKXWriteResGroup223 : SchedWriteRes<[SKXPort0,SKXPort23]> {
let Latency = 22;
@@ -5828,13 +5840,14 @@ def SKXWriteResGroup225 : SchedWriteRes<
def: InstRW<[SKXWriteResGroup225], (instregex "VPCONFLICTDZ128rr",
"VPCONFLICTQZ256rr")>;
-def SKXWriteResGroup226 : SchedWriteRes<[SKXPort0,SKXPort23]> {
+def SKXWriteResGroup226 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
let Latency = 23;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,6];
}
-def: InstRW<[SKXWriteResGroup226], (instregex "(V?)SQRTSDm")>;
+def: InstRW<[SKXWriteResGroup226], (instregex "(V?)SQRTSD(Z?)m")>;
+// FIXME
def SKXWriteResGroup227 : SchedWriteRes<[SKXPort0,SKXPort015]> {
let Latency = 23;
let NumMicroOps = 3;
@@ -5850,16 +5863,14 @@ def SKXWriteResGroup228 : SchedWriteRes<
}
def: InstRW<[SKXWriteResGroup228], (instregex "CMPXCHG16B")>;
-def SKXWriteResGroup229 : SchedWriteRes<[SKXPort0,SKXPort23]> {
+def SKXWriteResGroup229 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
let Latency = 24;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,6];
}
-def: InstRW<[SKXWriteResGroup229], (instregex "SQRTPDm",
- "VSQRTPDZ128m(b?)",
- "VSQRTPDm",
- "VSQRTSDZm")>;
+def: InstRW<[SKXWriteResGroup229], (instregex "(V?)SQRTPD(Z128)?m")>;
+//FIXME
def SKXWriteResGroup230 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> {
let Latency = 24;
let NumMicroOps = 4;
@@ -5867,13 +5878,12 @@ def SKXWriteResGroup230 : SchedWriteRes<
}
def: InstRW<[SKXWriteResGroup230], (instregex "VDIVPSZrm(b?)")>;
-def SKXWriteResGroup232 : SchedWriteRes<[SKXPort0,SKXPort23]> {
+def SKXWriteResGroup232 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
let Latency = 25;
let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let ResourceCycles = [1,1,12];
}
-def: InstRW<[SKXWriteResGroup232], (instregex "VSQRTPDYm",
- "VSQRTPDZ256m(b?)")>;
+def: InstRW<[SKXWriteResGroup232], (instregex "VSQRTPD(Y|Z256)m")>;
def SKXWriteResGroup233 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
let Latency = 25;
@@ -5894,6 +5904,7 @@ def: InstRW<[SKXWriteResGroup234], (inst
VPGATHERQDZrm,
VPGATHERQQZ256rm)>;
+// FIXME
def SKXWriteResGroup237 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> {
let Latency = 26;
let NumMicroOps = 4;
@@ -5949,6 +5960,7 @@ def SKXWriteResGroup243 : SchedWriteRes<
def: InstRW<[SKXWriteResGroup243], (instregex "DIVR_FI16m",
"DIVR_FI32m")>;
+// FIXME
def SKXWriteResGroup244 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> {
let Latency = 30;
let NumMicroOps = 4;
@@ -5964,6 +5976,7 @@ def SKXWriteResGroup245 : SchedWriteRes<
def: InstRW<[SKXWriteResGroup245], (instrs VGATHERDPSZrm,
VPGATHERDDZrm)>;
+// FIXME
def SKXWriteResGroup246 : SchedWriteRes<[SKXPort0,SKXPort015]> {
let Latency = 31;
let NumMicroOps = 3;
@@ -6002,6 +6015,7 @@ def SKXWriteResGroup250 : SchedWriteRes<
}
def: InstRW<[SKXWriteResGroup250], (instregex "XRSTOR(64)?")>;
+// FIXME
def SKXWriteResGroup251 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> {
let Latency = 38;
let NumMicroOps = 4;
Modified: llvm/trunk/test/CodeGen/X86/avx-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-schedule.ll?rev=328960&r1=328959&r2=328960&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-schedule.ll Sun Apr 1 22:33:28 2018
@@ -1498,38 +1498,38 @@ define <8 x i32> @test_cvttps2dq(<8 x fl
define <4 x double> @test_divpd(<4 x double> %a0, <4 x double> %a1, <4 x double> *%a2) {
; GENERIC-LABEL: test_divpd:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: vdivpd %ymm1, %ymm0, %ymm0 # sched: [45:2.00]
-; GENERIC-NEXT: vdivpd (%rdi), %ymm0, %ymm0 # sched: [52:2.00]
+; GENERIC-NEXT: vdivpd %ymm1, %ymm0, %ymm0 # sched: [45:44.00]
+; GENERIC-NEXT: vdivpd (%rdi), %ymm0, %ymm0 # sched: [52:44.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SANDY-LABEL: test_divpd:
; SANDY: # %bb.0:
-; SANDY-NEXT: vdivpd %ymm1, %ymm0, %ymm0 # sched: [45:2.00]
-; SANDY-NEXT: vdivpd (%rdi), %ymm0, %ymm0 # sched: [52:2.00]
+; SANDY-NEXT: vdivpd %ymm1, %ymm0, %ymm0 # sched: [45:44.00]
+; SANDY-NEXT: vdivpd (%rdi), %ymm0, %ymm0 # sched: [52:44.00]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_divpd:
; HASWELL: # %bb.0:
-; HASWELL-NEXT: vdivpd %ymm1, %ymm0, %ymm0 # sched: [35:2.00]
-; HASWELL-NEXT: vdivpd (%rdi), %ymm0, %ymm0 # sched: [42:2.00]
+; HASWELL-NEXT: vdivpd %ymm1, %ymm0, %ymm0 # sched: [35:28.00]
+; HASWELL-NEXT: vdivpd (%rdi), %ymm0, %ymm0 # sched: [42:28.00]
; HASWELL-NEXT: retq # sched: [7:1.00]
;
; BROADWELL-LABEL: test_divpd:
; BROADWELL: # %bb.0:
-; BROADWELL-NEXT: vdivpd %ymm1, %ymm0, %ymm0 # sched: [23:2.00]
-; BROADWELL-NEXT: vdivpd (%rdi), %ymm0, %ymm0 # sched: [29:2.00]
+; BROADWELL-NEXT: vdivpd %ymm1, %ymm0, %ymm0 # sched: [23:16.00]
+; BROADWELL-NEXT: vdivpd (%rdi), %ymm0, %ymm0 # sched: [29:16.00]
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_divpd:
; SKYLAKE: # %bb.0:
-; SKYLAKE-NEXT: vdivpd %ymm1, %ymm0, %ymm0 # sched: [14:1.00]
-; SKYLAKE-NEXT: vdivpd (%rdi), %ymm0, %ymm0 # sched: [21:1.00]
+; SKYLAKE-NEXT: vdivpd %ymm1, %ymm0, %ymm0 # sched: [14:5.00]
+; SKYLAKE-NEXT: vdivpd (%rdi), %ymm0, %ymm0 # sched: [21:8.00]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_divpd:
; SKX: # %bb.0:
-; SKX-NEXT: vdivpd %ymm1, %ymm0, %ymm0 # sched: [14:1.00]
-; SKX-NEXT: vdivpd (%rdi), %ymm0, %ymm0 # sched: [21:1.00]
+; SKX-NEXT: vdivpd %ymm1, %ymm0, %ymm0 # sched: [14:5.00]
+; SKX-NEXT: vdivpd (%rdi), %ymm0, %ymm0 # sched: [21:8.00]
; SKX-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_divpd:
@@ -1552,38 +1552,38 @@ define <4 x double> @test_divpd(<4 x dou
define <8 x float> @test_divps(<8 x float> %a0, <8 x float> %a1, <8 x float> *%a2) {
; GENERIC-LABEL: test_divps:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: vdivps %ymm1, %ymm0, %ymm0 # sched: [29:2.00]
-; GENERIC-NEXT: vdivps (%rdi), %ymm0, %ymm0 # sched: [36:2.00]
+; GENERIC-NEXT: vdivps %ymm1, %ymm0, %ymm0 # sched: [29:28.00]
+; GENERIC-NEXT: vdivps (%rdi), %ymm0, %ymm0 # sched: [36:28.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SANDY-LABEL: test_divps:
; SANDY: # %bb.0:
-; SANDY-NEXT: vdivps %ymm1, %ymm0, %ymm0 # sched: [29:2.00]
-; SANDY-NEXT: vdivps (%rdi), %ymm0, %ymm0 # sched: [36:2.00]
+; SANDY-NEXT: vdivps %ymm1, %ymm0, %ymm0 # sched: [29:28.00]
+; SANDY-NEXT: vdivps (%rdi), %ymm0, %ymm0 # sched: [36:28.00]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_divps:
; HASWELL: # %bb.0:
-; HASWELL-NEXT: vdivps %ymm1, %ymm0, %ymm0 # sched: [21:2.00]
-; HASWELL-NEXT: vdivps (%rdi), %ymm0, %ymm0 # sched: [28:2.00]
+; HASWELL-NEXT: vdivps %ymm1, %ymm0, %ymm0 # sched: [21:14.00]
+; HASWELL-NEXT: vdivps (%rdi), %ymm0, %ymm0 # sched: [28:14.00]
; HASWELL-NEXT: retq # sched: [7:1.00]
;
; BROADWELL-LABEL: test_divps:
; BROADWELL: # %bb.0:
-; BROADWELL-NEXT: vdivps %ymm1, %ymm0, %ymm0 # sched: [17:2.00]
-; BROADWELL-NEXT: vdivps (%rdi), %ymm0, %ymm0 # sched: [23:2.00]
+; BROADWELL-NEXT: vdivps %ymm1, %ymm0, %ymm0 # sched: [17:10.00]
+; BROADWELL-NEXT: vdivps (%rdi), %ymm0, %ymm0 # sched: [23:10.00]
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_divps:
; SKYLAKE: # %bb.0:
-; SKYLAKE-NEXT: vdivps %ymm1, %ymm0, %ymm0 # sched: [11:1.00]
-; SKYLAKE-NEXT: vdivps (%rdi), %ymm0, %ymm0 # sched: [18:1.00]
+; SKYLAKE-NEXT: vdivps %ymm1, %ymm0, %ymm0 # sched: [11:5.00]
+; SKYLAKE-NEXT: vdivps (%rdi), %ymm0, %ymm0 # sched: [18:5.00]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_divps:
; SKX: # %bb.0:
-; SKX-NEXT: vdivps %ymm1, %ymm0, %ymm0 # sched: [11:1.00]
-; SKX-NEXT: vdivps (%rdi), %ymm0, %ymm0 # sched: [18:1.00]
+; SKX-NEXT: vdivps %ymm1, %ymm0, %ymm0 # sched: [11:5.00]
+; SKX-NEXT: vdivps (%rdi), %ymm0, %ymm0 # sched: [18:5.00]
; SKX-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_divps:
@@ -4401,43 +4401,43 @@ define <8 x float> @test_shufps(<8 x flo
define <4 x double> @test_sqrtpd(<4 x double> %a0, <4 x double> *%a1) {
; GENERIC-LABEL: test_sqrtpd:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: vsqrtpd (%rdi), %ymm1 # sched: [52:2.00]
-; GENERIC-NEXT: vsqrtpd %ymm0, %ymm0 # sched: [45:2.00]
+; GENERIC-NEXT: vsqrtpd (%rdi), %ymm1 # sched: [52:44.00]
+; GENERIC-NEXT: vsqrtpd %ymm0, %ymm0 # sched: [45:44.00]
; GENERIC-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SANDY-LABEL: test_sqrtpd:
; SANDY: # %bb.0:
-; SANDY-NEXT: vsqrtpd (%rdi), %ymm1 # sched: [52:2.00]
-; SANDY-NEXT: vsqrtpd %ymm0, %ymm0 # sched: [45:2.00]
+; SANDY-NEXT: vsqrtpd (%rdi), %ymm1 # sched: [52:44.00]
+; SANDY-NEXT: vsqrtpd %ymm0, %ymm0 # sched: [45:44.00]
; SANDY-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_sqrtpd:
; HASWELL: # %bb.0:
-; HASWELL-NEXT: vsqrtpd (%rdi), %ymm1 # sched: [42:2.00]
-; HASWELL-NEXT: vsqrtpd %ymm0, %ymm0 # sched: [35:2.00]
+; HASWELL-NEXT: vsqrtpd (%rdi), %ymm1 # sched: [42:28.00]
+; HASWELL-NEXT: vsqrtpd %ymm0, %ymm0 # sched: [35:28.00]
; HASWELL-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
; HASWELL-NEXT: retq # sched: [7:1.00]
;
; BROADWELL-LABEL: test_sqrtpd:
; BROADWELL: # %bb.0:
-; BROADWELL-NEXT: vsqrtpd %ymm0, %ymm0 # sched: [34:2.00]
-; BROADWELL-NEXT: vsqrtpd (%rdi), %ymm1 # sched: [40:2.00]
+; BROADWELL-NEXT: vsqrtpd %ymm0, %ymm0 # sched: [29:28.00]
+; BROADWELL-NEXT: vsqrtpd (%rdi), %ymm1 # sched: [35:28.00]
; BROADWELL-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_sqrtpd:
; SKYLAKE: # %bb.0:
-; SKYLAKE-NEXT: vsqrtpd %ymm0, %ymm0 # sched: [18:1.00]
-; SKYLAKE-NEXT: vsqrtpd (%rdi), %ymm1 # sched: [25:1.00]
+; SKYLAKE-NEXT: vsqrtpd %ymm0, %ymm0 # sched: [18:12.00]
+; SKYLAKE-NEXT: vsqrtpd (%rdi), %ymm1 # sched: [25:12.00]
; SKYLAKE-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_sqrtpd:
; SKX: # %bb.0:
-; SKX-NEXT: vsqrtpd %ymm0, %ymm0 # sched: [18:1.00]
-; SKX-NEXT: vsqrtpd (%rdi), %ymm1 # sched: [25:1.00]
+; SKX-NEXT: vsqrtpd %ymm0, %ymm0 # sched: [18:12.00]
+; SKX-NEXT: vsqrtpd (%rdi), %ymm1 # sched: [25:12.00]
; SKX-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
; SKX-NEXT: retq # sched: [7:1.00]
;
@@ -4465,43 +4465,43 @@ declare <4 x double> @llvm.x86.avx.sqrt.
define <8 x float> @test_sqrtps(<8 x float> %a0, <8 x float> *%a1) {
; GENERIC-LABEL: test_sqrtps:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: vsqrtps (%rdi), %ymm1 # sched: [36:2.00]
-; GENERIC-NEXT: vsqrtps %ymm0, %ymm0 # sched: [29:2.00]
+; GENERIC-NEXT: vsqrtps (%rdi), %ymm1 # sched: [36:28.00]
+; GENERIC-NEXT: vsqrtps %ymm0, %ymm0 # sched: [29:28.00]
; GENERIC-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SANDY-LABEL: test_sqrtps:
; SANDY: # %bb.0:
-; SANDY-NEXT: vsqrtps (%rdi), %ymm1 # sched: [36:2.00]
-; SANDY-NEXT: vsqrtps %ymm0, %ymm0 # sched: [29:2.00]
+; SANDY-NEXT: vsqrtps (%rdi), %ymm1 # sched: [36:28.00]
+; SANDY-NEXT: vsqrtps %ymm0, %ymm0 # sched: [29:28.00]
; SANDY-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_sqrtps:
; HASWELL: # %bb.0:
-; HASWELL-NEXT: vsqrtps (%rdi), %ymm1 # sched: [28:2.00]
-; HASWELL-NEXT: vsqrtps %ymm0, %ymm0 # sched: [21:2.00]
+; HASWELL-NEXT: vsqrtps (%rdi), %ymm1 # sched: [28:14.00]
+; HASWELL-NEXT: vsqrtps %ymm0, %ymm0 # sched: [21:14.00]
; HASWELL-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
; HASWELL-NEXT: retq # sched: [7:1.00]
;
; BROADWELL-LABEL: test_sqrtps:
; BROADWELL: # %bb.0:
-; BROADWELL-NEXT: vsqrtps %ymm0, %ymm0 # sched: [21:2.00]
-; BROADWELL-NEXT: vsqrtps (%rdi), %ymm1 # sched: [27:2.00]
+; BROADWELL-NEXT: vsqrtps %ymm0, %ymm0 # sched: [21:14.00]
+; BROADWELL-NEXT: vsqrtps (%rdi), %ymm1 # sched: [27:14.00]
; BROADWELL-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_sqrtps:
; SKYLAKE: # %bb.0:
-; SKYLAKE-NEXT: vsqrtps %ymm0, %ymm0 # sched: [12:1.00]
-; SKYLAKE-NEXT: vsqrtps (%rdi), %ymm1 # sched: [19:1.00]
+; SKYLAKE-NEXT: vsqrtps %ymm0, %ymm0 # sched: [12:6.00]
+; SKYLAKE-NEXT: vsqrtps (%rdi), %ymm1 # sched: [19:6.00]
; SKYLAKE-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_sqrtps:
; SKX: # %bb.0:
-; SKX-NEXT: vsqrtps %ymm0, %ymm0 # sched: [12:1.00]
-; SKX-NEXT: vsqrtps (%rdi), %ymm1 # sched: [19:1.00]
+; SKX-NEXT: vsqrtps %ymm0, %ymm0 # sched: [12:6.00]
+; SKX-NEXT: vsqrtps (%rdi), %ymm1 # sched: [19:6.00]
; SKX-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
; SKX-NEXT: retq # sched: [7:1.00]
;
Modified: llvm/trunk/test/CodeGen/X86/avx512-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-schedule.ll?rev=328960&r1=328959&r2=328960&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-schedule.ll Sun Apr 1 22:33:28 2018
@@ -553,12 +553,12 @@ declare float @sqrtf(float) readnone
define float @sqrtA(float %a) nounwind uwtable readnone ssp {
; GENERIC-LABEL: sqrtA:
; GENERIC: # %bb.0: # %entry
-; GENERIC-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # sched: [14:1.00]
+; GENERIC-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # sched: [14:14.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: sqrtA:
; SKX: # %bb.0: # %entry
-; SKX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # sched: [12:1.00]
+; SKX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # sched: [12:3.00]
; SKX-NEXT: retq # sched: [7:1.00]
entry:
%conv1 = tail call float @sqrtf(float %a) nounwind readnone
@@ -569,12 +569,12 @@ declare double @sqrt(double) readnone
define double @sqrtB(double %a) nounwind uwtable readnone ssp {
; GENERIC-LABEL: sqrtB:
; GENERIC: # %bb.0: # %entry
-; GENERIC-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 # sched: [21:1.00]
+; GENERIC-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 # sched: [21:21.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: sqrtB:
; SKX: # %bb.0: # %entry
-; SKX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 # sched: [18:1.00]
+; SKX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 # sched: [18:6.00]
; SKX-NEXT: retq # sched: [7:1.00]
entry:
%call = tail call double @sqrt(double %a) nounwind readnone
@@ -585,12 +585,12 @@ declare float @llvm.sqrt.f32(float)
define float @sqrtC(float %a) nounwind {
; GENERIC-LABEL: sqrtC:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # sched: [14:1.00]
+; GENERIC-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # sched: [14:14.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: sqrtC:
; SKX: # %bb.0:
-; SKX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # sched: [12:1.00]
+; SKX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # sched: [12:3.00]
; SKX-NEXT: retq # sched: [7:1.00]
%b = call float @llvm.sqrt.f32(float %a)
ret float %b
Modified: llvm/trunk/test/CodeGen/X86/recip-fastmath.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/recip-fastmath.ll?rev=328960&r1=328959&r2=328960&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/recip-fastmath.ll (original)
+++ llvm/trunk/test/CodeGen/X86/recip-fastmath.ll Sun Apr 1 22:33:28 2018
@@ -46,13 +46,13 @@ define float @f32_no_estimate(float %x)
; SANDY-LABEL: f32_no_estimate:
; SANDY: # %bb.0:
; SANDY-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [6:0.50]
-; SANDY-NEXT: vdivss %xmm0, %xmm1, %xmm0 # sched: [14:1.00]
+; SANDY-NEXT: vdivss %xmm0, %xmm1, %xmm0 # sched: [14:14.00]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: f32_no_estimate:
; HASWELL: # %bb.0:
; HASWELL-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [5:0.50]
-; HASWELL-NEXT: vdivss %xmm0, %xmm1, %xmm0 # sched: [13:1.00]
+; HASWELL-NEXT: vdivss %xmm0, %xmm1, %xmm0 # sched: [13:7.00]
; HASWELL-NEXT: retq # sched: [7:1.00]
;
; HASWELL-NO-FMA-LABEL: f32_no_estimate:
@@ -64,13 +64,13 @@ define float @f32_no_estimate(float %x)
; KNL-LABEL: f32_no_estimate:
; KNL: # %bb.0:
; KNL-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [5:0.50]
-; KNL-NEXT: vdivss %xmm0, %xmm1, %xmm0 # sched: [13:1.00]
+; KNL-NEXT: vdivss %xmm0, %xmm1, %xmm0 # sched: [13:7.00]
; KNL-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: f32_no_estimate:
; SKX: # %bb.0:
; SKX-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [5:0.50]
-; SKX-NEXT: vdivss %xmm0, %xmm1, %xmm0 # sched: [11:1.00]
+; SKX-NEXT: vdivss %xmm0, %xmm1, %xmm0 # sched: [11:3.00]
; SKX-NEXT: retq # sched: [7:1.00]
%div = fdiv fast float 1.0, %x
ret float %div
@@ -309,13 +309,13 @@ define <4 x float> @v4f32_no_estimate(<4
; SANDY-LABEL: v4f32_no_estimate:
; SANDY: # %bb.0:
; SANDY-NEXT: vmovaps {{.*#+}} xmm1 = [1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00] sched: [6:0.50]
-; SANDY-NEXT: vdivps %xmm0, %xmm1, %xmm0 # sched: [14:1.00]
+; SANDY-NEXT: vdivps %xmm0, %xmm1, %xmm0 # sched: [14:14.00]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: v4f32_no_estimate:
; HASWELL: # %bb.0:
; HASWELL-NEXT: vbroadcastss {{.*#+}} xmm1 = [1,1,1,1] sched: [6:0.50]
-; HASWELL-NEXT: vdivps %xmm0, %xmm1, %xmm0 # sched: [13:1.00]
+; HASWELL-NEXT: vdivps %xmm0, %xmm1, %xmm0 # sched: [13:7.00]
; HASWELL-NEXT: retq # sched: [7:1.00]
;
; HASWELL-NO-FMA-LABEL: v4f32_no_estimate:
@@ -327,13 +327,13 @@ define <4 x float> @v4f32_no_estimate(<4
; KNL-LABEL: v4f32_no_estimate:
; KNL: # %bb.0:
; KNL-NEXT: vbroadcastss {{.*#+}} xmm1 = [1,1,1,1] sched: [6:0.50]
-; KNL-NEXT: vdivps %xmm0, %xmm1, %xmm0 # sched: [13:1.00]
+; KNL-NEXT: vdivps %xmm0, %xmm1, %xmm0 # sched: [13:7.00]
; KNL-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: v4f32_no_estimate:
; SKX: # %bb.0:
; SKX-NEXT: vbroadcastss {{.*#+}} xmm1 = [1,1,1,1] sched: [6:0.50]
-; SKX-NEXT: vdivps %xmm0, %xmm1, %xmm0 # sched: [11:1.00]
+; SKX-NEXT: vdivps %xmm0, %xmm1, %xmm0 # sched: [11:3.00]
; SKX-NEXT: retq # sched: [7:1.00]
%div = fdiv fast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, %x
ret <4 x float> %div
@@ -577,13 +577,13 @@ define <8 x float> @v8f32_no_estimate(<8
; SANDY-LABEL: v8f32_no_estimate:
; SANDY: # %bb.0:
; SANDY-NEXT: vmovaps {{.*#+}} ymm1 = [1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00] sched: [7:0.50]
-; SANDY-NEXT: vdivps %ymm0, %ymm1, %ymm0 # sched: [29:2.00]
+; SANDY-NEXT: vdivps %ymm0, %ymm1, %ymm0 # sched: [29:28.00]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: v8f32_no_estimate:
; HASWELL: # %bb.0:
; HASWELL-NEXT: vbroadcastss {{.*#+}} ymm1 = [1,1,1,1,1,1,1,1] sched: [7:0.50]
-; HASWELL-NEXT: vdivps %ymm0, %ymm1, %ymm0 # sched: [21:2.00]
+; HASWELL-NEXT: vdivps %ymm0, %ymm1, %ymm0 # sched: [21:14.00]
; HASWELL-NEXT: retq # sched: [7:1.00]
;
; HASWELL-NO-FMA-LABEL: v8f32_no_estimate:
@@ -595,13 +595,13 @@ define <8 x float> @v8f32_no_estimate(<8
; KNL-LABEL: v8f32_no_estimate:
; KNL: # %bb.0:
; KNL-NEXT: vbroadcastss {{.*#+}} ymm1 = [1,1,1,1,1,1,1,1] sched: [7:0.50]
-; KNL-NEXT: vdivps %ymm0, %ymm1, %ymm0 # sched: [21:2.00]
+; KNL-NEXT: vdivps %ymm0, %ymm1, %ymm0 # sched: [21:14.00]
; KNL-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: v8f32_no_estimate:
; SKX: # %bb.0:
; SKX-NEXT: vbroadcastss {{.*#+}} ymm1 = [1,1,1,1,1,1,1,1] sched: [7:0.50]
-; SKX-NEXT: vdivps %ymm0, %ymm1, %ymm0 # sched: [11:1.00]
+; SKX-NEXT: vdivps %ymm0, %ymm1, %ymm0 # sched: [11:5.00]
; SKX-NEXT: retq # sched: [7:1.00]
%div = fdiv fast <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %x
ret <8 x float> %div
Modified: llvm/trunk/test/CodeGen/X86/sse-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-schedule.ll?rev=328960&r1=328959&r2=328960&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse-schedule.ll Sun Apr 1 22:33:28 2018
@@ -1723,8 +1723,8 @@ define i64 @test_cvttss2siq(float %a0, f
define <4 x float> @test_divps(<4 x float> %a0, <4 x float> %a1, <4 x float> *%a2) {
; GENERIC-LABEL: test_divps:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: divps %xmm1, %xmm0 # sched: [14:1.00]
-; GENERIC-NEXT: divps (%rdi), %xmm0 # sched: [20:1.00]
+; GENERIC-NEXT: divps %xmm1, %xmm0 # sched: [14:14.00]
+; GENERIC-NEXT: divps (%rdi), %xmm0 # sched: [20:14.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; ATOM-LABEL: test_divps:
@@ -1741,62 +1741,62 @@ define <4 x float> @test_divps(<4 x floa
;
; SANDY-SSE-LABEL: test_divps:
; SANDY-SSE: # %bb.0:
-; SANDY-SSE-NEXT: divps %xmm1, %xmm0 # sched: [14:1.00]
-; SANDY-SSE-NEXT: divps (%rdi), %xmm0 # sched: [20:1.00]
+; SANDY-SSE-NEXT: divps %xmm1, %xmm0 # sched: [14:14.00]
+; SANDY-SSE-NEXT: divps (%rdi), %xmm0 # sched: [20:14.00]
; SANDY-SSE-NEXT: retq # sched: [1:1.00]
;
; SANDY-LABEL: test_divps:
; SANDY: # %bb.0:
-; SANDY-NEXT: vdivps %xmm1, %xmm0, %xmm0 # sched: [14:1.00]
-; SANDY-NEXT: vdivps (%rdi), %xmm0, %xmm0 # sched: [20:1.00]
+; SANDY-NEXT: vdivps %xmm1, %xmm0, %xmm0 # sched: [14:14.00]
+; SANDY-NEXT: vdivps (%rdi), %xmm0, %xmm0 # sched: [20:14.00]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-SSE-LABEL: test_divps:
; HASWELL-SSE: # %bb.0:
-; HASWELL-SSE-NEXT: divps %xmm1, %xmm0 # sched: [13:1.00]
-; HASWELL-SSE-NEXT: divps (%rdi), %xmm0 # sched: [19:1.00]
+; HASWELL-SSE-NEXT: divps %xmm1, %xmm0 # sched: [13:7.00]
+; HASWELL-SSE-NEXT: divps (%rdi), %xmm0 # sched: [19:7.00]
; HASWELL-SSE-NEXT: retq # sched: [7:1.00]
;
; HASWELL-LABEL: test_divps:
; HASWELL: # %bb.0:
-; HASWELL-NEXT: vdivps %xmm1, %xmm0, %xmm0 # sched: [13:1.00]
-; HASWELL-NEXT: vdivps (%rdi), %xmm0, %xmm0 # sched: [19:1.00]
+; HASWELL-NEXT: vdivps %xmm1, %xmm0, %xmm0 # sched: [13:7.00]
+; HASWELL-NEXT: vdivps (%rdi), %xmm0, %xmm0 # sched: [19:7.00]
; HASWELL-NEXT: retq # sched: [7:1.00]
;
; BROADWELL-SSE-LABEL: test_divps:
; BROADWELL-SSE: # %bb.0:
-; BROADWELL-SSE-NEXT: divps %xmm1, %xmm0 # sched: [11:1.00]
-; BROADWELL-SSE-NEXT: divps (%rdi), %xmm0 # sched: [16:1.00]
+; BROADWELL-SSE-NEXT: divps %xmm1, %xmm0 # sched: [11:5.00]
+; BROADWELL-SSE-NEXT: divps (%rdi), %xmm0 # sched: [16:5.00]
; BROADWELL-SSE-NEXT: retq # sched: [7:1.00]
;
; BROADWELL-LABEL: test_divps:
; BROADWELL: # %bb.0:
-; BROADWELL-NEXT: vdivps %xmm1, %xmm0, %xmm0 # sched: [11:1.00]
-; BROADWELL-NEXT: vdivps (%rdi), %xmm0, %xmm0 # sched: [16:1.00]
+; BROADWELL-NEXT: vdivps %xmm1, %xmm0, %xmm0 # sched: [11:5.00]
+; BROADWELL-NEXT: vdivps (%rdi), %xmm0, %xmm0 # sched: [16:5.00]
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-SSE-LABEL: test_divps:
; SKYLAKE-SSE: # %bb.0:
-; SKYLAKE-SSE-NEXT: divps %xmm1, %xmm0 # sched: [11:1.00]
-; SKYLAKE-SSE-NEXT: divps (%rdi), %xmm0 # sched: [17:1.00]
+; SKYLAKE-SSE-NEXT: divps %xmm1, %xmm0 # sched: [11:3.00]
+; SKYLAKE-SSE-NEXT: divps (%rdi), %xmm0 # sched: [17:5.00]
; SKYLAKE-SSE-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_divps:
; SKYLAKE: # %bb.0:
-; SKYLAKE-NEXT: vdivps %xmm1, %xmm0, %xmm0 # sched: [11:1.00]
-; SKYLAKE-NEXT: vdivps (%rdi), %xmm0, %xmm0 # sched: [17:1.00]
+; SKYLAKE-NEXT: vdivps %xmm1, %xmm0, %xmm0 # sched: [11:3.00]
+; SKYLAKE-NEXT: vdivps (%rdi), %xmm0, %xmm0 # sched: [17:5.00]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-SSE-LABEL: test_divps:
; SKX-SSE: # %bb.0:
-; SKX-SSE-NEXT: divps %xmm1, %xmm0 # sched: [11:1.00]
-; SKX-SSE-NEXT: divps (%rdi), %xmm0 # sched: [17:1.00]
+; SKX-SSE-NEXT: divps %xmm1, %xmm0 # sched: [11:3.00]
+; SKX-SSE-NEXT: divps (%rdi), %xmm0 # sched: [17:5.00]
; SKX-SSE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_divps:
; SKX: # %bb.0:
-; SKX-NEXT: vdivps %xmm1, %xmm0, %xmm0 # sched: [11:1.00]
-; SKX-NEXT: vdivps (%rdi), %xmm0, %xmm0 # sched: [17:1.00]
+; SKX-NEXT: vdivps %xmm1, %xmm0, %xmm0 # sched: [11:3.00]
+; SKX-NEXT: vdivps (%rdi), %xmm0, %xmm0 # sched: [17:5.00]
; SKX-NEXT: retq # sched: [7:1.00]
;
; BTVER2-SSE-LABEL: test_divps:
@@ -1831,8 +1831,8 @@ define <4 x float> @test_divps(<4 x floa
define float @test_divss(float %a0, float %a1, float *%a2) {
; GENERIC-LABEL: test_divss:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: divss %xmm1, %xmm0 # sched: [14:1.00]
-; GENERIC-NEXT: divss (%rdi), %xmm0 # sched: [20:1.00]
+; GENERIC-NEXT: divss %xmm1, %xmm0 # sched: [14:14.00]
+; GENERIC-NEXT: divss (%rdi), %xmm0 # sched: [20:14.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; ATOM-LABEL: test_divss:
@@ -1849,62 +1849,62 @@ define float @test_divss(float %a0, floa
;
; SANDY-SSE-LABEL: test_divss:
; SANDY-SSE: # %bb.0:
-; SANDY-SSE-NEXT: divss %xmm1, %xmm0 # sched: [14:1.00]
-; SANDY-SSE-NEXT: divss (%rdi), %xmm0 # sched: [20:1.00]
+; SANDY-SSE-NEXT: divss %xmm1, %xmm0 # sched: [14:14.00]
+; SANDY-SSE-NEXT: divss (%rdi), %xmm0 # sched: [20:14.00]
; SANDY-SSE-NEXT: retq # sched: [1:1.00]
;
; SANDY-LABEL: test_divss:
; SANDY: # %bb.0:
-; SANDY-NEXT: vdivss %xmm1, %xmm0, %xmm0 # sched: [14:1.00]
-; SANDY-NEXT: vdivss (%rdi), %xmm0, %xmm0 # sched: [20:1.00]
+; SANDY-NEXT: vdivss %xmm1, %xmm0, %xmm0 # sched: [14:14.00]
+; SANDY-NEXT: vdivss (%rdi), %xmm0, %xmm0 # sched: [20:14.00]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-SSE-LABEL: test_divss:
; HASWELL-SSE: # %bb.0:
-; HASWELL-SSE-NEXT: divss %xmm1, %xmm0 # sched: [13:1.00]
-; HASWELL-SSE-NEXT: divss (%rdi), %xmm0 # sched: [18:1.00]
+; HASWELL-SSE-NEXT: divss %xmm1, %xmm0 # sched: [13:7.00]
+; HASWELL-SSE-NEXT: divss (%rdi), %xmm0 # sched: [18:7.00]
; HASWELL-SSE-NEXT: retq # sched: [7:1.00]
;
; HASWELL-LABEL: test_divss:
; HASWELL: # %bb.0:
-; HASWELL-NEXT: vdivss %xmm1, %xmm0, %xmm0 # sched: [13:1.00]
-; HASWELL-NEXT: vdivss (%rdi), %xmm0, %xmm0 # sched: [18:1.00]
+; HASWELL-NEXT: vdivss %xmm1, %xmm0, %xmm0 # sched: [13:7.00]
+; HASWELL-NEXT: vdivss (%rdi), %xmm0, %xmm0 # sched: [18:7.00]
; HASWELL-NEXT: retq # sched: [7:1.00]
;
; BROADWELL-SSE-LABEL: test_divss:
; BROADWELL-SSE: # %bb.0:
-; BROADWELL-SSE-NEXT: divss %xmm1, %xmm0 # sched: [11:1.00]
-; BROADWELL-SSE-NEXT: divss (%rdi), %xmm0 # sched: [16:1.00]
+; BROADWELL-SSE-NEXT: divss %xmm1, %xmm0 # sched: [11:3.00]
+; BROADWELL-SSE-NEXT: divss (%rdi), %xmm0 # sched: [16:5.00]
; BROADWELL-SSE-NEXT: retq # sched: [7:1.00]
;
; BROADWELL-LABEL: test_divss:
; BROADWELL: # %bb.0:
-; BROADWELL-NEXT: vdivss %xmm1, %xmm0, %xmm0 # sched: [11:1.00]
-; BROADWELL-NEXT: vdivss (%rdi), %xmm0, %xmm0 # sched: [16:1.00]
+; BROADWELL-NEXT: vdivss %xmm1, %xmm0, %xmm0 # sched: [11:3.00]
+; BROADWELL-NEXT: vdivss (%rdi), %xmm0, %xmm0 # sched: [16:5.00]
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-SSE-LABEL: test_divss:
; SKYLAKE-SSE: # %bb.0:
-; SKYLAKE-SSE-NEXT: divss %xmm1, %xmm0 # sched: [11:1.00]
-; SKYLAKE-SSE-NEXT: divss (%rdi), %xmm0 # sched: [16:1.00]
+; SKYLAKE-SSE-NEXT: divss %xmm1, %xmm0 # sched: [11:3.00]
+; SKYLAKE-SSE-NEXT: divss (%rdi), %xmm0 # sched: [16:3.00]
; SKYLAKE-SSE-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_divss:
; SKYLAKE: # %bb.0:
-; SKYLAKE-NEXT: vdivss %xmm1, %xmm0, %xmm0 # sched: [11:1.00]
-; SKYLAKE-NEXT: vdivss (%rdi), %xmm0, %xmm0 # sched: [16:1.00]
+; SKYLAKE-NEXT: vdivss %xmm1, %xmm0, %xmm0 # sched: [11:3.00]
+; SKYLAKE-NEXT: vdivss (%rdi), %xmm0, %xmm0 # sched: [16:3.00]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-SSE-LABEL: test_divss:
; SKX-SSE: # %bb.0:
-; SKX-SSE-NEXT: divss %xmm1, %xmm0 # sched: [11:1.00]
-; SKX-SSE-NEXT: divss (%rdi), %xmm0 # sched: [16:1.00]
+; SKX-SSE-NEXT: divss %xmm1, %xmm0 # sched: [11:3.00]
+; SKX-SSE-NEXT: divss (%rdi), %xmm0 # sched: [16:3.00]
; SKX-SSE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_divss:
; SKX: # %bb.0:
-; SKX-NEXT: vdivss %xmm1, %xmm0, %xmm0 # sched: [11:1.00]
-; SKX-NEXT: vdivss (%rdi), %xmm0, %xmm0 # sched: [16:1.00]
+; SKX-NEXT: vdivss %xmm1, %xmm0, %xmm0 # sched: [11:3.00]
+; SKX-NEXT: vdivss (%rdi), %xmm0, %xmm0 # sched: [16:3.00]
; SKX-NEXT: retq # sched: [7:1.00]
;
; BTVER2-SSE-LABEL: test_divss:
@@ -4900,8 +4900,8 @@ define <4 x float> @test_shufps(<4 x flo
define <4 x float> @test_sqrtps(<4 x float> %a0, <4 x float> *%a1) {
; GENERIC-LABEL: test_sqrtps:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: sqrtps %xmm0, %xmm1 # sched: [14:1.00]
-; GENERIC-NEXT: sqrtps (%rdi), %xmm0 # sched: [20:1.00]
+; GENERIC-NEXT: sqrtps %xmm0, %xmm1 # sched: [14:14.00]
+; GENERIC-NEXT: sqrtps (%rdi), %xmm0 # sched: [20:14.00]
; GENERIC-NEXT: addps %xmm1, %xmm0 # sched: [3:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@@ -4922,71 +4922,71 @@ define <4 x float> @test_sqrtps(<4 x flo
;
; SANDY-SSE-LABEL: test_sqrtps:
; SANDY-SSE: # %bb.0:
-; SANDY-SSE-NEXT: sqrtps %xmm0, %xmm1 # sched: [14:1.00]
-; SANDY-SSE-NEXT: sqrtps (%rdi), %xmm0 # sched: [20:1.00]
+; SANDY-SSE-NEXT: sqrtps %xmm0, %xmm1 # sched: [14:14.00]
+; SANDY-SSE-NEXT: sqrtps (%rdi), %xmm0 # sched: [20:14.00]
; SANDY-SSE-NEXT: addps %xmm1, %xmm0 # sched: [3:1.00]
; SANDY-SSE-NEXT: retq # sched: [1:1.00]
;
; SANDY-LABEL: test_sqrtps:
; SANDY: # %bb.0:
-; SANDY-NEXT: vsqrtps %xmm0, %xmm0 # sched: [14:1.00]
-; SANDY-NEXT: vsqrtps (%rdi), %xmm1 # sched: [20:1.00]
+; SANDY-NEXT: vsqrtps %xmm0, %xmm0 # sched: [14:14.00]
+; SANDY-NEXT: vsqrtps (%rdi), %xmm1 # sched: [20:14.00]
; SANDY-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-SSE-LABEL: test_sqrtps:
; HASWELL-SSE: # %bb.0:
-; HASWELL-SSE-NEXT: sqrtps %xmm0, %xmm1 # sched: [11:1.00]
-; HASWELL-SSE-NEXT: sqrtps (%rdi), %xmm0 # sched: [17:1.00]
+; HASWELL-SSE-NEXT: sqrtps %xmm0, %xmm1 # sched: [11:7.00]
+; HASWELL-SSE-NEXT: sqrtps (%rdi), %xmm0 # sched: [17:7.00]
; HASWELL-SSE-NEXT: addps %xmm1, %xmm0 # sched: [3:1.00]
; HASWELL-SSE-NEXT: retq # sched: [7:1.00]
;
; HASWELL-LABEL: test_sqrtps:
; HASWELL: # %bb.0:
-; HASWELL-NEXT: vsqrtps %xmm0, %xmm0 # sched: [11:1.00]
-; HASWELL-NEXT: vsqrtps (%rdi), %xmm1 # sched: [17:1.00]
+; HASWELL-NEXT: vsqrtps %xmm0, %xmm0 # sched: [11:7.00]
+; HASWELL-NEXT: vsqrtps (%rdi), %xmm1 # sched: [17:7.00]
; HASWELL-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; HASWELL-NEXT: retq # sched: [7:1.00]
;
; BROADWELL-SSE-LABEL: test_sqrtps:
; BROADWELL-SSE: # %bb.0:
-; BROADWELL-SSE-NEXT: sqrtps %xmm0, %xmm1 # sched: [11:1.00]
-; BROADWELL-SSE-NEXT: sqrtps (%rdi), %xmm0 # sched: [16:1.00]
+; BROADWELL-SSE-NEXT: sqrtps %xmm0, %xmm1 # sched: [11:7.00]
+; BROADWELL-SSE-NEXT: sqrtps (%rdi), %xmm0 # sched: [16:7.00]
; BROADWELL-SSE-NEXT: addps %xmm1, %xmm0 # sched: [3:1.00]
; BROADWELL-SSE-NEXT: retq # sched: [7:1.00]
;
; BROADWELL-LABEL: test_sqrtps:
; BROADWELL: # %bb.0:
-; BROADWELL-NEXT: vsqrtps %xmm0, %xmm0 # sched: [11:1.00]
-; BROADWELL-NEXT: vsqrtps (%rdi), %xmm1 # sched: [16:1.00]
+; BROADWELL-NEXT: vsqrtps %xmm0, %xmm0 # sched: [11:7.00]
+; BROADWELL-NEXT: vsqrtps (%rdi), %xmm1 # sched: [16:7.00]
; BROADWELL-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-SSE-LABEL: test_sqrtps:
; SKYLAKE-SSE: # %bb.0:
-; SKYLAKE-SSE-NEXT: sqrtps %xmm0, %xmm1 # sched: [12:1.00]
-; SKYLAKE-SSE-NEXT: sqrtps (%rdi), %xmm0 # sched: [18:1.00]
+; SKYLAKE-SSE-NEXT: sqrtps %xmm0, %xmm1 # sched: [12:3.00]
+; SKYLAKE-SSE-NEXT: sqrtps (%rdi), %xmm0 # sched: [18:3.00]
; SKYLAKE-SSE-NEXT: addps %xmm1, %xmm0 # sched: [4:0.50]
; SKYLAKE-SSE-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_sqrtps:
; SKYLAKE: # %bb.0:
-; SKYLAKE-NEXT: vsqrtps %xmm0, %xmm0 # sched: [12:1.00]
-; SKYLAKE-NEXT: vsqrtps (%rdi), %xmm1 # sched: [18:1.00]
+; SKYLAKE-NEXT: vsqrtps %xmm0, %xmm0 # sched: [12:3.00]
+; SKYLAKE-NEXT: vsqrtps (%rdi), %xmm1 # sched: [18:3.00]
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-SSE-LABEL: test_sqrtps:
; SKX-SSE: # %bb.0:
-; SKX-SSE-NEXT: sqrtps %xmm0, %xmm1 # sched: [12:1.00]
-; SKX-SSE-NEXT: sqrtps (%rdi), %xmm0 # sched: [18:1.00]
+; SKX-SSE-NEXT: sqrtps %xmm0, %xmm1 # sched: [12:3.00]
+; SKX-SSE-NEXT: sqrtps (%rdi), %xmm0 # sched: [18:3.00]
; SKX-SSE-NEXT: addps %xmm1, %xmm0 # sched: [4:0.33]
; SKX-SSE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_sqrtps:
; SKX: # %bb.0:
-; SKX-NEXT: vsqrtps %xmm0, %xmm0 # sched: [12:1.00]
-; SKX-NEXT: vsqrtps (%rdi), %xmm1 # sched: [18:1.00]
+; SKX-NEXT: vsqrtps %xmm0, %xmm0 # sched: [12:3.00]
+; SKX-NEXT: vsqrtps (%rdi), %xmm1 # sched: [18:3.00]
; SKX-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
; SKX-NEXT: retq # sched: [7:1.00]
;
@@ -5030,9 +5030,9 @@ declare <4 x float> @llvm.x86.sse.sqrt.p
define <4 x float> @test_sqrtss(<4 x float> %a0, <4 x float> *%a1) {
; GENERIC-LABEL: test_sqrtss:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: sqrtss %xmm0, %xmm0 # sched: [14:1.00]
+; GENERIC-NEXT: sqrtss %xmm0, %xmm0 # sched: [14:14.00]
; GENERIC-NEXT: movaps (%rdi), %xmm1 # sched: [6:0.50]
-; GENERIC-NEXT: sqrtss %xmm1, %xmm1 # sched: [14:1.00]
+; GENERIC-NEXT: sqrtss %xmm1, %xmm1 # sched: [14:14.00]
; GENERIC-NEXT: addps %xmm1, %xmm0 # sched: [3:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@@ -5054,81 +5054,81 @@ define <4 x float> @test_sqrtss(<4 x flo
;
; SANDY-SSE-LABEL: test_sqrtss:
; SANDY-SSE: # %bb.0:
-; SANDY-SSE-NEXT: sqrtss %xmm0, %xmm0 # sched: [14:1.00]
+; SANDY-SSE-NEXT: sqrtss %xmm0, %xmm0 # sched: [14:14.00]
; SANDY-SSE-NEXT: movaps (%rdi), %xmm1 # sched: [6:0.50]
-; SANDY-SSE-NEXT: sqrtss %xmm1, %xmm1 # sched: [14:1.00]
+; SANDY-SSE-NEXT: sqrtss %xmm1, %xmm1 # sched: [14:14.00]
; SANDY-SSE-NEXT: addps %xmm1, %xmm0 # sched: [3:1.00]
; SANDY-SSE-NEXT: retq # sched: [1:1.00]
;
; SANDY-LABEL: test_sqrtss:
; SANDY: # %bb.0:
-; SANDY-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # sched: [14:1.00]
+; SANDY-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # sched: [14:14.00]
; SANDY-NEXT: vmovaps (%rdi), %xmm1 # sched: [6:0.50]
-; SANDY-NEXT: vsqrtss %xmm1, %xmm1, %xmm1 # sched: [14:1.00]
+; SANDY-NEXT: vsqrtss %xmm1, %xmm1, %xmm1 # sched: [14:14.00]
; SANDY-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-SSE-LABEL: test_sqrtss:
; HASWELL-SSE: # %bb.0:
-; HASWELL-SSE-NEXT: sqrtss %xmm0, %xmm0 # sched: [11:1.00]
+; HASWELL-SSE-NEXT: sqrtss %xmm0, %xmm0 # sched: [11:7.00]
; HASWELL-SSE-NEXT: movaps (%rdi), %xmm1 # sched: [6:0.50]
-; HASWELL-SSE-NEXT: sqrtss %xmm1, %xmm1 # sched: [11:1.00]
+; HASWELL-SSE-NEXT: sqrtss %xmm1, %xmm1 # sched: [11:7.00]
; HASWELL-SSE-NEXT: addps %xmm1, %xmm0 # sched: [3:1.00]
; HASWELL-SSE-NEXT: retq # sched: [7:1.00]
;
; HASWELL-LABEL: test_sqrtss:
; HASWELL: # %bb.0:
-; HASWELL-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # sched: [11:1.00]
+; HASWELL-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # sched: [11:7.00]
; HASWELL-NEXT: vmovaps (%rdi), %xmm1 # sched: [6:0.50]
-; HASWELL-NEXT: vsqrtss %xmm1, %xmm1, %xmm1 # sched: [11:1.00]
+; HASWELL-NEXT: vsqrtss %xmm1, %xmm1, %xmm1 # sched: [11:7.00]
; HASWELL-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; HASWELL-NEXT: retq # sched: [7:1.00]
;
; BROADWELL-SSE-LABEL: test_sqrtss:
; BROADWELL-SSE: # %bb.0:
-; BROADWELL-SSE-NEXT: sqrtss %xmm0, %xmm0 # sched: [11:1.00]
+; BROADWELL-SSE-NEXT: sqrtss %xmm0, %xmm0 # sched: [11:4.00]
; BROADWELL-SSE-NEXT: movaps (%rdi), %xmm1 # sched: [5:0.50]
-; BROADWELL-SSE-NEXT: sqrtss %xmm1, %xmm1 # sched: [11:1.00]
+; BROADWELL-SSE-NEXT: sqrtss %xmm1, %xmm1 # sched: [11:4.00]
; BROADWELL-SSE-NEXT: addps %xmm1, %xmm0 # sched: [3:1.00]
; BROADWELL-SSE-NEXT: retq # sched: [7:1.00]
;
; BROADWELL-LABEL: test_sqrtss:
; BROADWELL: # %bb.0:
-; BROADWELL-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # sched: [11:1.00]
+; BROADWELL-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # sched: [11:4.00]
; BROADWELL-NEXT: vmovaps (%rdi), %xmm1 # sched: [5:0.50]
-; BROADWELL-NEXT: vsqrtss %xmm1, %xmm1, %xmm1 # sched: [11:1.00]
+; BROADWELL-NEXT: vsqrtss %xmm1, %xmm1, %xmm1 # sched: [11:4.00]
; BROADWELL-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-SSE-LABEL: test_sqrtss:
; SKYLAKE-SSE: # %bb.0:
-; SKYLAKE-SSE-NEXT: sqrtss %xmm0, %xmm0 # sched: [12:1.00]
+; SKYLAKE-SSE-NEXT: sqrtss %xmm0, %xmm0 # sched: [12:3.00]
; SKYLAKE-SSE-NEXT: movaps (%rdi), %xmm1 # sched: [6:0.50]
-; SKYLAKE-SSE-NEXT: sqrtss %xmm1, %xmm1 # sched: [12:1.00]
+; SKYLAKE-SSE-NEXT: sqrtss %xmm1, %xmm1 # sched: [12:3.00]
; SKYLAKE-SSE-NEXT: addps %xmm1, %xmm0 # sched: [4:0.50]
; SKYLAKE-SSE-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_sqrtss:
; SKYLAKE: # %bb.0:
-; SKYLAKE-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # sched: [12:1.00]
+; SKYLAKE-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # sched: [12:3.00]
; SKYLAKE-NEXT: vmovaps (%rdi), %xmm1 # sched: [6:0.50]
-; SKYLAKE-NEXT: vsqrtss %xmm1, %xmm1, %xmm1 # sched: [12:1.00]
+; SKYLAKE-NEXT: vsqrtss %xmm1, %xmm1, %xmm1 # sched: [12:3.00]
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-SSE-LABEL: test_sqrtss:
; SKX-SSE: # %bb.0:
-; SKX-SSE-NEXT: sqrtss %xmm0, %xmm0 # sched: [12:1.00]
+; SKX-SSE-NEXT: sqrtss %xmm0, %xmm0 # sched: [12:3.00]
; SKX-SSE-NEXT: movaps (%rdi), %xmm1 # sched: [6:0.50]
-; SKX-SSE-NEXT: sqrtss %xmm1, %xmm1 # sched: [12:1.00]
+; SKX-SSE-NEXT: sqrtss %xmm1, %xmm1 # sched: [12:3.00]
; SKX-SSE-NEXT: addps %xmm1, %xmm0 # sched: [4:0.33]
; SKX-SSE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_sqrtss:
; SKX: # %bb.0:
-; SKX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # sched: [12:1.00]
+; SKX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # sched: [12:3.00]
; SKX-NEXT: vmovaps (%rdi), %xmm1 # sched: [6:0.50]
-; SKX-NEXT: vsqrtss %xmm1, %xmm1, %xmm1 # sched: [12:1.00]
+; SKX-NEXT: vsqrtss %xmm1, %xmm1, %xmm1 # sched: [12:3.00]
; SKX-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
; SKX-NEXT: retq # sched: [7:1.00]
;
Modified: llvm/trunk/test/CodeGen/X86/sse2-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-schedule.ll?rev=328960&r1=328959&r2=328960&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse2-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse2-schedule.ll Sun Apr 1 22:33:28 2018
@@ -3164,8 +3164,8 @@ define i64 @test_cvttsd2siq(double %a0,
define <2 x double> @test_divpd(<2 x double> %a0, <2 x double> %a1, <2 x double> *%a2) {
; GENERIC-LABEL: test_divpd:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: divpd %xmm1, %xmm0 # sched: [22:1.00]
-; GENERIC-NEXT: divpd (%rdi), %xmm0 # sched: [28:1.00]
+; GENERIC-NEXT: divpd %xmm1, %xmm0 # sched: [22:22.00]
+; GENERIC-NEXT: divpd (%rdi), %xmm0 # sched: [28:22.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; ATOM-LABEL: test_divpd:
@@ -3182,62 +3182,62 @@ define <2 x double> @test_divpd(<2 x dou
;
; SANDY-SSE-LABEL: test_divpd:
; SANDY-SSE: # %bb.0:
-; SANDY-SSE-NEXT: divpd %xmm1, %xmm0 # sched: [22:1.00]
-; SANDY-SSE-NEXT: divpd (%rdi), %xmm0 # sched: [28:1.00]
+; SANDY-SSE-NEXT: divpd %xmm1, %xmm0 # sched: [22:22.00]
+; SANDY-SSE-NEXT: divpd (%rdi), %xmm0 # sched: [28:22.00]
; SANDY-SSE-NEXT: retq # sched: [1:1.00]
;
; SANDY-LABEL: test_divpd:
; SANDY: # %bb.0:
-; SANDY-NEXT: vdivpd %xmm1, %xmm0, %xmm0 # sched: [22:1.00]
-; SANDY-NEXT: vdivpd (%rdi), %xmm0, %xmm0 # sched: [28:1.00]
+; SANDY-NEXT: vdivpd %xmm1, %xmm0, %xmm0 # sched: [22:22.00]
+; SANDY-NEXT: vdivpd (%rdi), %xmm0, %xmm0 # sched: [28:22.00]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-SSE-LABEL: test_divpd:
; HASWELL-SSE: # %bb.0:
-; HASWELL-SSE-NEXT: divpd %xmm1, %xmm0 # sched: [20:1.00]
-; HASWELL-SSE-NEXT: divpd (%rdi), %xmm0 # sched: [26:1.00]
+; HASWELL-SSE-NEXT: divpd %xmm1, %xmm0 # sched: [20:14.00]
+; HASWELL-SSE-NEXT: divpd (%rdi), %xmm0 # sched: [26:14.00]
; HASWELL-SSE-NEXT: retq # sched: [7:1.00]
;
; HASWELL-LABEL: test_divpd:
; HASWELL: # %bb.0:
-; HASWELL-NEXT: vdivpd %xmm1, %xmm0, %xmm0 # sched: [20:1.00]
-; HASWELL-NEXT: vdivpd (%rdi), %xmm0, %xmm0 # sched: [26:1.00]
+; HASWELL-NEXT: vdivpd %xmm1, %xmm0, %xmm0 # sched: [20:14.00]
+; HASWELL-NEXT: vdivpd (%rdi), %xmm0, %xmm0 # sched: [26:14.00]
; HASWELL-NEXT: retq # sched: [7:1.00]
;
; BROADWELL-SSE-LABEL: test_divpd:
; BROADWELL-SSE: # %bb.0:
-; BROADWELL-SSE-NEXT: divpd %xmm1, %xmm0 # sched: [14:1.00]
-; BROADWELL-SSE-NEXT: divpd (%rdi), %xmm0 # sched: [19:1.00]
+; BROADWELL-SSE-NEXT: divpd %xmm1, %xmm0 # sched: [14:8.00]
+; BROADWELL-SSE-NEXT: divpd (%rdi), %xmm0 # sched: [19:8.00]
; BROADWELL-SSE-NEXT: retq # sched: [7:1.00]
;
; BROADWELL-LABEL: test_divpd:
; BROADWELL: # %bb.0:
-; BROADWELL-NEXT: vdivpd %xmm1, %xmm0, %xmm0 # sched: [14:1.00]
-; BROADWELL-NEXT: vdivpd (%rdi), %xmm0, %xmm0 # sched: [19:1.00]
+; BROADWELL-NEXT: vdivpd %xmm1, %xmm0, %xmm0 # sched: [14:8.00]
+; BROADWELL-NEXT: vdivpd (%rdi), %xmm0, %xmm0 # sched: [19:8.00]
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-SSE-LABEL: test_divpd:
; SKYLAKE-SSE: # %bb.0:
-; SKYLAKE-SSE-NEXT: divpd %xmm1, %xmm0 # sched: [14:1.00]
-; SKYLAKE-SSE-NEXT: divpd (%rdi), %xmm0 # sched: [20:1.00]
+; SKYLAKE-SSE-NEXT: divpd %xmm1, %xmm0 # sched: [14:3.00]
+; SKYLAKE-SSE-NEXT: divpd (%rdi), %xmm0 # sched: [20:4.00]
; SKYLAKE-SSE-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_divpd:
; SKYLAKE: # %bb.0:
-; SKYLAKE-NEXT: vdivpd %xmm1, %xmm0, %xmm0 # sched: [14:1.00]
-; SKYLAKE-NEXT: vdivpd (%rdi), %xmm0, %xmm0 # sched: [20:1.00]
+; SKYLAKE-NEXT: vdivpd %xmm1, %xmm0, %xmm0 # sched: [14:3.00]
+; SKYLAKE-NEXT: vdivpd (%rdi), %xmm0, %xmm0 # sched: [20:4.00]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-SSE-LABEL: test_divpd:
; SKX-SSE: # %bb.0:
-; SKX-SSE-NEXT: divpd %xmm1, %xmm0 # sched: [14:1.00]
-; SKX-SSE-NEXT: divpd (%rdi), %xmm0 # sched: [20:1.00]
+; SKX-SSE-NEXT: divpd %xmm1, %xmm0 # sched: [14:3.00]
+; SKX-SSE-NEXT: divpd (%rdi), %xmm0 # sched: [20:4.00]
; SKX-SSE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_divpd:
; SKX: # %bb.0:
-; SKX-NEXT: vdivpd %xmm1, %xmm0, %xmm0 # sched: [14:1.00]
-; SKX-NEXT: vdivpd (%rdi), %xmm0, %xmm0 # sched: [20:1.00]
+; SKX-NEXT: vdivpd %xmm1, %xmm0, %xmm0 # sched: [14:3.00]
+; SKX-NEXT: vdivpd (%rdi), %xmm0, %xmm0 # sched: [20:4.00]
; SKX-NEXT: retq # sched: [7:1.00]
;
; BTVER2-SSE-LABEL: test_divpd:
@@ -3272,8 +3272,8 @@ define <2 x double> @test_divpd(<2 x dou
define double @test_divsd(double %a0, double %a1, double *%a2) {
; GENERIC-LABEL: test_divsd:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: divsd %xmm1, %xmm0 # sched: [22:1.00]
-; GENERIC-NEXT: divsd (%rdi), %xmm0 # sched: [28:1.00]
+; GENERIC-NEXT: divsd %xmm1, %xmm0 # sched: [22:22.00]
+; GENERIC-NEXT: divsd (%rdi), %xmm0 # sched: [28:22.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; ATOM-LABEL: test_divsd:
@@ -3290,62 +3290,62 @@ define double @test_divsd(double %a0, do
;
; SANDY-SSE-LABEL: test_divsd:
; SANDY-SSE: # %bb.0:
-; SANDY-SSE-NEXT: divsd %xmm1, %xmm0 # sched: [22:1.00]
-; SANDY-SSE-NEXT: divsd (%rdi), %xmm0 # sched: [28:1.00]
+; SANDY-SSE-NEXT: divsd %xmm1, %xmm0 # sched: [22:22.00]
+; SANDY-SSE-NEXT: divsd (%rdi), %xmm0 # sched: [28:22.00]
; SANDY-SSE-NEXT: retq # sched: [1:1.00]
;
; SANDY-LABEL: test_divsd:
; SANDY: # %bb.0:
-; SANDY-NEXT: vdivsd %xmm1, %xmm0, %xmm0 # sched: [22:1.00]
-; SANDY-NEXT: vdivsd (%rdi), %xmm0, %xmm0 # sched: [28:1.00]
+; SANDY-NEXT: vdivsd %xmm1, %xmm0, %xmm0 # sched: [22:22.00]
+; SANDY-NEXT: vdivsd (%rdi), %xmm0, %xmm0 # sched: [28:22.00]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-SSE-LABEL: test_divsd:
; HASWELL-SSE: # %bb.0:
-; HASWELL-SSE-NEXT: divsd %xmm1, %xmm0 # sched: [20:1.00]
-; HASWELL-SSE-NEXT: divsd (%rdi), %xmm0 # sched: [25:1.00]
+; HASWELL-SSE-NEXT: divsd %xmm1, %xmm0 # sched: [20:14.00]
+; HASWELL-SSE-NEXT: divsd (%rdi), %xmm0 # sched: [25:14.00]
; HASWELL-SSE-NEXT: retq # sched: [7:1.00]
;
; HASWELL-LABEL: test_divsd:
; HASWELL: # %bb.0:
-; HASWELL-NEXT: vdivsd %xmm1, %xmm0, %xmm0 # sched: [20:1.00]
-; HASWELL-NEXT: vdivsd (%rdi), %xmm0, %xmm0 # sched: [25:1.00]
+; HASWELL-NEXT: vdivsd %xmm1, %xmm0, %xmm0 # sched: [20:14.00]
+; HASWELL-NEXT: vdivsd (%rdi), %xmm0, %xmm0 # sched: [25:14.00]
; HASWELL-NEXT: retq # sched: [7:1.00]
;
; BROADWELL-SSE-LABEL: test_divsd:
; BROADWELL-SSE: # %bb.0:
-; BROADWELL-SSE-NEXT: divsd %xmm1, %xmm0 # sched: [14:1.00]
-; BROADWELL-SSE-NEXT: divsd (%rdi), %xmm0 # sched: [19:1.00]
+; BROADWELL-SSE-NEXT: divsd %xmm1, %xmm0 # sched: [14:4.00]
+; BROADWELL-SSE-NEXT: divsd (%rdi), %xmm0 # sched: [19:8.00]
; BROADWELL-SSE-NEXT: retq # sched: [7:1.00]
;
; BROADWELL-LABEL: test_divsd:
; BROADWELL: # %bb.0:
-; BROADWELL-NEXT: vdivsd %xmm1, %xmm0, %xmm0 # sched: [14:1.00]
-; BROADWELL-NEXT: vdivsd (%rdi), %xmm0, %xmm0 # sched: [19:1.00]
+; BROADWELL-NEXT: vdivsd %xmm1, %xmm0, %xmm0 # sched: [14:4.00]
+; BROADWELL-NEXT: vdivsd (%rdi), %xmm0, %xmm0 # sched: [19:8.00]
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-SSE-LABEL: test_divsd:
; SKYLAKE-SSE: # %bb.0:
-; SKYLAKE-SSE-NEXT: divsd %xmm1, %xmm0 # sched: [14:1.00]
-; SKYLAKE-SSE-NEXT: divsd (%rdi), %xmm0 # sched: [19:1.00]
+; SKYLAKE-SSE-NEXT: divsd %xmm1, %xmm0 # sched: [14:3.00]
+; SKYLAKE-SSE-NEXT: divsd (%rdi), %xmm0 # sched: [19:4.00]
; SKYLAKE-SSE-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_divsd:
; SKYLAKE: # %bb.0:
-; SKYLAKE-NEXT: vdivsd %xmm1, %xmm0, %xmm0 # sched: [14:1.00]
-; SKYLAKE-NEXT: vdivsd (%rdi), %xmm0, %xmm0 # sched: [19:1.00]
+; SKYLAKE-NEXT: vdivsd %xmm1, %xmm0, %xmm0 # sched: [14:3.00]
+; SKYLAKE-NEXT: vdivsd (%rdi), %xmm0, %xmm0 # sched: [19:4.00]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-SSE-LABEL: test_divsd:
; SKX-SSE: # %bb.0:
-; SKX-SSE-NEXT: divsd %xmm1, %xmm0 # sched: [14:1.00]
-; SKX-SSE-NEXT: divsd (%rdi), %xmm0 # sched: [19:1.00]
+; SKX-SSE-NEXT: divsd %xmm1, %xmm0 # sched: [14:3.00]
+; SKX-SSE-NEXT: divsd (%rdi), %xmm0 # sched: [19:4.00]
; SKX-SSE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_divsd:
; SKX: # %bb.0:
-; SKX-NEXT: vdivsd %xmm1, %xmm0, %xmm0 # sched: [14:1.00]
-; SKX-NEXT: vdivsd (%rdi), %xmm0, %xmm0 # sched: [19:1.00]
+; SKX-NEXT: vdivsd %xmm1, %xmm0, %xmm0 # sched: [14:3.00]
+; SKX-NEXT: vdivsd (%rdi), %xmm0, %xmm0 # sched: [19:4.00]
; SKX-NEXT: retq # sched: [7:1.00]
;
; BTVER2-SSE-LABEL: test_divsd:
@@ -14142,8 +14142,8 @@ define <2 x double> @test_shufpd(<2 x do
define <2 x double> @test_sqrtpd(<2 x double> %a0, <2 x double> *%a1) {
; GENERIC-LABEL: test_sqrtpd:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: sqrtpd %xmm0, %xmm1 # sched: [21:1.00]
-; GENERIC-NEXT: sqrtpd (%rdi), %xmm0 # sched: [27:1.00]
+; GENERIC-NEXT: sqrtpd %xmm0, %xmm1 # sched: [21:21.00]
+; GENERIC-NEXT: sqrtpd (%rdi), %xmm0 # sched: [27:21.00]
; GENERIC-NEXT: addpd %xmm1, %xmm0 # sched: [3:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@@ -14164,71 +14164,71 @@ define <2 x double> @test_sqrtpd(<2 x do
;
; SANDY-SSE-LABEL: test_sqrtpd:
; SANDY-SSE: # %bb.0:
-; SANDY-SSE-NEXT: sqrtpd %xmm0, %xmm1 # sched: [21:1.00]
-; SANDY-SSE-NEXT: sqrtpd (%rdi), %xmm0 # sched: [27:1.00]
+; SANDY-SSE-NEXT: sqrtpd %xmm0, %xmm1 # sched: [21:21.00]
+; SANDY-SSE-NEXT: sqrtpd (%rdi), %xmm0 # sched: [27:21.00]
; SANDY-SSE-NEXT: addpd %xmm1, %xmm0 # sched: [3:1.00]
; SANDY-SSE-NEXT: retq # sched: [1:1.00]
;
; SANDY-LABEL: test_sqrtpd:
; SANDY: # %bb.0:
-; SANDY-NEXT: vsqrtpd %xmm0, %xmm0 # sched: [21:1.00]
-; SANDY-NEXT: vsqrtpd (%rdi), %xmm1 # sched: [27:1.00]
+; SANDY-NEXT: vsqrtpd %xmm0, %xmm0 # sched: [21:21.00]
+; SANDY-NEXT: vsqrtpd (%rdi), %xmm1 # sched: [27:21.00]
; SANDY-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-SSE-LABEL: test_sqrtpd:
; HASWELL-SSE: # %bb.0:
-; HASWELL-SSE-NEXT: sqrtpd %xmm0, %xmm1 # sched: [16:1.00]
-; HASWELL-SSE-NEXT: sqrtpd (%rdi), %xmm0 # sched: [22:1.00]
+; HASWELL-SSE-NEXT: sqrtpd %xmm0, %xmm1 # sched: [16:14.00]
+; HASWELL-SSE-NEXT: sqrtpd (%rdi), %xmm0 # sched: [22:14.00]
; HASWELL-SSE-NEXT: addpd %xmm1, %xmm0 # sched: [3:1.00]
; HASWELL-SSE-NEXT: retq # sched: [7:1.00]
;
; HASWELL-LABEL: test_sqrtpd:
; HASWELL: # %bb.0:
-; HASWELL-NEXT: vsqrtpd %xmm0, %xmm0 # sched: [16:1.00]
-; HASWELL-NEXT: vsqrtpd (%rdi), %xmm1 # sched: [22:1.00]
+; HASWELL-NEXT: vsqrtpd %xmm0, %xmm0 # sched: [16:14.00]
+; HASWELL-NEXT: vsqrtpd (%rdi), %xmm1 # sched: [22:14.00]
; HASWELL-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; HASWELL-NEXT: retq # sched: [7:1.00]
;
; BROADWELL-SSE-LABEL: test_sqrtpd:
; BROADWELL-SSE: # %bb.0:
-; BROADWELL-SSE-NEXT: sqrtpd %xmm0, %xmm1 # sched: [16:1.00]
-; BROADWELL-SSE-NEXT: sqrtpd (%rdi), %xmm0 # sched: [21:1.00]
+; BROADWELL-SSE-NEXT: sqrtpd %xmm0, %xmm1 # sched: [16:14.00]
+; BROADWELL-SSE-NEXT: sqrtpd (%rdi), %xmm0 # sched: [21:14.00]
; BROADWELL-SSE-NEXT: addpd %xmm1, %xmm0 # sched: [3:1.00]
; BROADWELL-SSE-NEXT: retq # sched: [7:1.00]
;
; BROADWELL-LABEL: test_sqrtpd:
; BROADWELL: # %bb.0:
-; BROADWELL-NEXT: vsqrtpd %xmm0, %xmm0 # sched: [16:1.00]
-; BROADWELL-NEXT: vsqrtpd (%rdi), %xmm1 # sched: [21:1.00]
+; BROADWELL-NEXT: vsqrtpd %xmm0, %xmm0 # sched: [16:14.00]
+; BROADWELL-NEXT: vsqrtpd (%rdi), %xmm1 # sched: [21:14.00]
; BROADWELL-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-SSE-LABEL: test_sqrtpd:
; SKYLAKE-SSE: # %bb.0:
-; SKYLAKE-SSE-NEXT: sqrtpd %xmm0, %xmm1 # sched: [18:1.00]
-; SKYLAKE-SSE-NEXT: sqrtpd (%rdi), %xmm0 # sched: [24:1.00]
+; SKYLAKE-SSE-NEXT: sqrtpd %xmm0, %xmm1 # sched: [18:6.00]
+; SKYLAKE-SSE-NEXT: sqrtpd (%rdi), %xmm0 # sched: [24:6.00]
; SKYLAKE-SSE-NEXT: addpd %xmm1, %xmm0 # sched: [4:0.50]
; SKYLAKE-SSE-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_sqrtpd:
; SKYLAKE: # %bb.0:
-; SKYLAKE-NEXT: vsqrtpd %xmm0, %xmm0 # sched: [18:1.00]
-; SKYLAKE-NEXT: vsqrtpd (%rdi), %xmm1 # sched: [24:1.00]
+; SKYLAKE-NEXT: vsqrtpd %xmm0, %xmm0 # sched: [18:6.00]
+; SKYLAKE-NEXT: vsqrtpd (%rdi), %xmm1 # sched: [24:6.00]
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-SSE-LABEL: test_sqrtpd:
; SKX-SSE: # %bb.0:
-; SKX-SSE-NEXT: sqrtpd %xmm0, %xmm1 # sched: [18:1.00]
-; SKX-SSE-NEXT: sqrtpd (%rdi), %xmm0 # sched: [24:1.00]
+; SKX-SSE-NEXT: sqrtpd %xmm0, %xmm1 # sched: [18:6.00]
+; SKX-SSE-NEXT: sqrtpd (%rdi), %xmm0 # sched: [24:6.00]
; SKX-SSE-NEXT: addpd %xmm1, %xmm0 # sched: [4:0.33]
; SKX-SSE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_sqrtpd:
; SKX: # %bb.0:
-; SKX-NEXT: vsqrtpd %xmm0, %xmm0 # sched: [18:1.00]
-; SKX-NEXT: vsqrtpd (%rdi), %xmm1 # sched: [24:1.00]
+; SKX-NEXT: vsqrtpd %xmm0, %xmm0 # sched: [18:6.00]
+; SKX-NEXT: vsqrtpd (%rdi), %xmm1 # sched: [24:6.00]
; SKX-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
; SKX-NEXT: retq # sched: [7:1.00]
;
@@ -14272,9 +14272,9 @@ declare <2 x double> @llvm.x86.sse2.sqrt
define <2 x double> @test_sqrtsd(<2 x double> %a0, <2 x double> *%a1) {
; GENERIC-LABEL: test_sqrtsd:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: sqrtsd %xmm0, %xmm0 # sched: [21:1.00]
+; GENERIC-NEXT: sqrtsd %xmm0, %xmm0 # sched: [21:21.00]
; GENERIC-NEXT: movapd (%rdi), %xmm1 # sched: [6:0.50]
-; GENERIC-NEXT: sqrtsd %xmm1, %xmm1 # sched: [21:1.00]
+; GENERIC-NEXT: sqrtsd %xmm1, %xmm1 # sched: [21:21.00]
; GENERIC-NEXT: addpd %xmm1, %xmm0 # sched: [3:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@@ -14296,81 +14296,81 @@ define <2 x double> @test_sqrtsd(<2 x do
;
; SANDY-SSE-LABEL: test_sqrtsd:
; SANDY-SSE: # %bb.0:
-; SANDY-SSE-NEXT: sqrtsd %xmm0, %xmm0 # sched: [21:1.00]
+; SANDY-SSE-NEXT: sqrtsd %xmm0, %xmm0 # sched: [21:21.00]
; SANDY-SSE-NEXT: movapd (%rdi), %xmm1 # sched: [6:0.50]
-; SANDY-SSE-NEXT: sqrtsd %xmm1, %xmm1 # sched: [21:1.00]
+; SANDY-SSE-NEXT: sqrtsd %xmm1, %xmm1 # sched: [21:21.00]
; SANDY-SSE-NEXT: addpd %xmm1, %xmm0 # sched: [3:1.00]
; SANDY-SSE-NEXT: retq # sched: [1:1.00]
;
; SANDY-LABEL: test_sqrtsd:
; SANDY: # %bb.0:
-; SANDY-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 # sched: [21:1.00]
+; SANDY-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 # sched: [21:21.00]
; SANDY-NEXT: vmovapd (%rdi), %xmm1 # sched: [6:0.50]
-; SANDY-NEXT: vsqrtsd %xmm1, %xmm1, %xmm1 # sched: [21:1.00]
+; SANDY-NEXT: vsqrtsd %xmm1, %xmm1, %xmm1 # sched: [21:21.00]
; SANDY-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-SSE-LABEL: test_sqrtsd:
; HASWELL-SSE: # %bb.0:
-; HASWELL-SSE-NEXT: sqrtsd %xmm0, %xmm0 # sched: [16:1.00]
+; HASWELL-SSE-NEXT: sqrtsd %xmm0, %xmm0 # sched: [16:14.00]
; HASWELL-SSE-NEXT: movapd (%rdi), %xmm1 # sched: [6:0.50]
-; HASWELL-SSE-NEXT: sqrtsd %xmm1, %xmm1 # sched: [16:1.00]
+; HASWELL-SSE-NEXT: sqrtsd %xmm1, %xmm1 # sched: [16:14.00]
; HASWELL-SSE-NEXT: addpd %xmm1, %xmm0 # sched: [3:1.00]
; HASWELL-SSE-NEXT: retq # sched: [7:1.00]
;
; HASWELL-LABEL: test_sqrtsd:
; HASWELL: # %bb.0:
-; HASWELL-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 # sched: [16:1.00]
+; HASWELL-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 # sched: [16:14.00]
; HASWELL-NEXT: vmovapd (%rdi), %xmm1 # sched: [6:0.50]
-; HASWELL-NEXT: vsqrtsd %xmm1, %xmm1, %xmm1 # sched: [16:1.00]
+; HASWELL-NEXT: vsqrtsd %xmm1, %xmm1, %xmm1 # sched: [16:14.00]
; HASWELL-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; HASWELL-NEXT: retq # sched: [7:1.00]
;
; BROADWELL-SSE-LABEL: test_sqrtsd:
; BROADWELL-SSE: # %bb.0:
-; BROADWELL-SSE-NEXT: sqrtsd %xmm0, %xmm0 # sched: [16:1.00]
+; BROADWELL-SSE-NEXT: sqrtsd %xmm0, %xmm0 # sched: [16:8.00]
; BROADWELL-SSE-NEXT: movapd (%rdi), %xmm1 # sched: [5:0.50]
-; BROADWELL-SSE-NEXT: sqrtsd %xmm1, %xmm1 # sched: [16:1.00]
+; BROADWELL-SSE-NEXT: sqrtsd %xmm1, %xmm1 # sched: [16:8.00]
; BROADWELL-SSE-NEXT: addpd %xmm1, %xmm0 # sched: [3:1.00]
; BROADWELL-SSE-NEXT: retq # sched: [7:1.00]
;
; BROADWELL-LABEL: test_sqrtsd:
; BROADWELL: # %bb.0:
-; BROADWELL-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 # sched: [16:1.00]
+; BROADWELL-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 # sched: [16:8.00]
; BROADWELL-NEXT: vmovapd (%rdi), %xmm1 # sched: [5:0.50]
-; BROADWELL-NEXT: vsqrtsd %xmm1, %xmm1, %xmm1 # sched: [16:1.00]
+; BROADWELL-NEXT: vsqrtsd %xmm1, %xmm1, %xmm1 # sched: [16:8.00]
; BROADWELL-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-SSE-LABEL: test_sqrtsd:
; SKYLAKE-SSE: # %bb.0:
-; SKYLAKE-SSE-NEXT: sqrtsd %xmm0, %xmm0 # sched: [18:1.00]
+; SKYLAKE-SSE-NEXT: sqrtsd %xmm0, %xmm0 # sched: [18:6.00]
; SKYLAKE-SSE-NEXT: movapd (%rdi), %xmm1 # sched: [6:0.50]
-; SKYLAKE-SSE-NEXT: sqrtsd %xmm1, %xmm1 # sched: [18:1.00]
+; SKYLAKE-SSE-NEXT: sqrtsd %xmm1, %xmm1 # sched: [18:6.00]
; SKYLAKE-SSE-NEXT: addpd %xmm1, %xmm0 # sched: [4:0.50]
; SKYLAKE-SSE-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_sqrtsd:
; SKYLAKE: # %bb.0:
-; SKYLAKE-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 # sched: [18:1.00]
+; SKYLAKE-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 # sched: [18:6.00]
; SKYLAKE-NEXT: vmovapd (%rdi), %xmm1 # sched: [6:0.50]
-; SKYLAKE-NEXT: vsqrtsd %xmm1, %xmm1, %xmm1 # sched: [18:1.00]
+; SKYLAKE-NEXT: vsqrtsd %xmm1, %xmm1, %xmm1 # sched: [18:6.00]
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-SSE-LABEL: test_sqrtsd:
; SKX-SSE: # %bb.0:
-; SKX-SSE-NEXT: sqrtsd %xmm0, %xmm0 # sched: [18:1.00]
+; SKX-SSE-NEXT: sqrtsd %xmm0, %xmm0 # sched: [18:6.00]
; SKX-SSE-NEXT: movapd (%rdi), %xmm1 # sched: [6:0.50]
-; SKX-SSE-NEXT: sqrtsd %xmm1, %xmm1 # sched: [18:1.00]
+; SKX-SSE-NEXT: sqrtsd %xmm1, %xmm1 # sched: [18:6.00]
; SKX-SSE-NEXT: addpd %xmm1, %xmm0 # sched: [4:0.33]
; SKX-SSE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_sqrtsd:
; SKX: # %bb.0:
-; SKX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 # sched: [18:1.00]
+; SKX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 # sched: [18:6.00]
; SKX-NEXT: vmovapd (%rdi), %xmm1 # sched: [6:0.50]
-; SKX-NEXT: vsqrtsd %xmm1, %xmm1, %xmm1 # sched: [18:1.00]
+; SKX-NEXT: vsqrtsd %xmm1, %xmm1, %xmm1 # sched: [18:6.00]
; SKX-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
; SKX-NEXT: retq # sched: [7:1.00]
;
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