[llvm] r328959 - [X86] Fix the SchedRW for AVX512 shift instructions.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 1 20:15:02 PDT 2018
Author: ctopper
Date: Sun Apr 1 20:15:02 2018
New Revision: 328959
URL: http://llvm.org/viewvc/llvm-project?rev=328959&view=rev
Log:
[X86] Fix the SchedRW for AVX512 shift instructions.
It was being inadvertently defaulted to an FADD scheduler class.
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/test/CodeGen/X86/avx512-schedule.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=328959&r1=328958&r2=328959&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Sun Apr 1 20:15:02 2018
@@ -5697,17 +5697,22 @@ multiclass avx512_var_shift_w<bits<8> op
}
}
-defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl, SSE_INTSHIFT_P>,
- avx512_var_shift_w<0x12, "vpsllvw", shl, SSE_INTSHIFT_P>;
+let Sched = WriteVarVecShift in
+def AVX512_VARSHIFT_P : OpndItins<
+ IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM
+>;
-defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra, SSE_INTSHIFT_P>,
- avx512_var_shift_w<0x11, "vpsravw", sra, SSE_INTSHIFT_P>;
+defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl, AVX512_VARSHIFT_P>,
+ avx512_var_shift_w<0x12, "vpsllvw", shl, AVX512_VARSHIFT_P>;
-defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl, SSE_INTSHIFT_P>,
- avx512_var_shift_w<0x10, "vpsrlvw", srl, SSE_INTSHIFT_P>;
+defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra, AVX512_VARSHIFT_P>,
+ avx512_var_shift_w<0x11, "vpsravw", sra, AVX512_VARSHIFT_P>;
-defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr, SSE_INTSHIFT_P>;
-defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl, SSE_INTSHIFT_P>;
+defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl, AVX512_VARSHIFT_P>,
+ avx512_var_shift_w<0x10, "vpsrlvw", srl, AVX512_VARSHIFT_P>;
+
+defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr, AVX512_VARSHIFT_P>;
+defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl, AVX512_VARSHIFT_P>;
defm : avx512_var_shift_lowering<avx512vl_i64_info, "VPSRAVQ", sra, [HasAVX512, NoVLX]>;
defm : avx512_var_shift_lowering<avx512vl_i16_info, "VPSLLVW", shl, [HasBWI, NoVLX]>;
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=328959&r1=328958&r2=328959&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sun Apr 1 20:15:02 2018
@@ -146,6 +146,7 @@ def SSE_INTMUL_ITINS_P : OpndItins<
>;
// FIXME: Merge SSE_INTSHIFT_P + SSE_INTSHIFT_ITINS_P.
+let Sched = WriteVecShift in
def SSE_INTSHIFT_P : OpndItins<
IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM
>;
Modified: llvm/trunk/test/CodeGen/X86/avx512-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-schedule.ll?rev=328959&r1=328958&r2=328959&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-schedule.ll Sun Apr 1 20:15:02 2018
@@ -2783,7 +2783,7 @@ define <16 x float> @ubto16f32(<16 x i32
; GENERIC: # %bb.0:
; GENERIC-NEXT: vpmovd2m %zmm0, %k0 # sched: [1:0.33]
; GENERIC-NEXT: vpmovm2d %k0, %zmm0 # sched: [1:0.33]
-; GENERIC-NEXT: vpsrld $31, %zmm0, %zmm0 # sched: [3:1.00]
+; GENERIC-NEXT: vpsrld $31, %zmm0, %zmm0 # sched: [1:1.00]
; GENERIC-NEXT: vcvtdq2ps %zmm0, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@@ -2804,7 +2804,7 @@ define <16 x double> @ubto16f64(<16 x i3
; GENERIC: # %bb.0:
; GENERIC-NEXT: vpmovd2m %zmm0, %k0 # sched: [1:0.33]
; GENERIC-NEXT: vpmovm2d %k0, %zmm0 # sched: [1:0.33]
-; GENERIC-NEXT: vpsrld $31, %zmm0, %zmm1 # sched: [3:1.00]
+; GENERIC-NEXT: vpsrld $31, %zmm0, %zmm1 # sched: [1:1.00]
; GENERIC-NEXT: vcvtdq2pd %ymm1, %zmm0 # sched: [4:1.00]
; GENERIC-NEXT: vextracti64x4 $1, %zmm1, %ymm1 # sched: [1:1.00]
; GENERIC-NEXT: vcvtdq2pd %ymm1, %zmm1 # sched: [4:1.00]
@@ -4246,7 +4246,7 @@ define <16 x i32> @zext_16i1_to_16xi32
; GENERIC: # %bb.0:
; GENERIC-NEXT: kmovd %edi, %k0 # sched: [1:0.33]
; GENERIC-NEXT: vpmovm2d %k0, %zmm0 # sched: [1:0.33]
-; GENERIC-NEXT: vpsrld $31, %zmm0, %zmm0 # sched: [3:1.00]
+; GENERIC-NEXT: vpsrld $31, %zmm0, %zmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: zext_16i1_to_16xi32:
@@ -4265,7 +4265,7 @@ define <8 x i64> @zext_8i1_to_8xi64(i8
; GENERIC: # %bb.0:
; GENERIC-NEXT: kmovd %edi, %k0 # sched: [1:0.33]
; GENERIC-NEXT: vpmovm2q %k0, %zmm0 # sched: [1:0.33]
-; GENERIC-NEXT: vpsrlq $63, %zmm0, %zmm0 # sched: [3:1.00]
+; GENERIC-NEXT: vpsrlq $63, %zmm0, %zmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: zext_8i1_to_8xi64:
@@ -4303,7 +4303,7 @@ define i16 @trunc_16i8_to_16i1(<16 x i8>
define i16 @trunc_16i32_to_16i1(<16 x i32> %a) {
; GENERIC-LABEL: trunc_16i32_to_16i1:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: vpslld $31, %zmm0, %zmm0 # sched: [3:1.00]
+; GENERIC-NEXT: vpslld $31, %zmm0, %zmm0 # sched: [1:1.00]
; GENERIC-NEXT: vpmovd2m %zmm0, %k0 # sched: [1:0.33]
; GENERIC-NEXT: kmovd %k0, %eax # sched: [1:0.33]
; GENERIC-NEXT: # kill: def $ax killed $ax killed $eax
@@ -4493,7 +4493,7 @@ define void @extload_v8i64(<8 x i8>* %a,
define <64 x i16> @test21(<64 x i16> %x , <64 x i1> %mask) nounwind readnone {
; GENERIC-LABEL: test21:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: vpsllw $7, %zmm2, %zmm2 # sched: [3:1.00]
+; GENERIC-NEXT: vpsllw $7, %zmm2, %zmm2 # sched: [1:1.00]
; GENERIC-NEXT: vpmovb2m %zmm2, %k1 # sched: [1:0.33]
; GENERIC-NEXT: vmovdqu16 %zmm0, %zmm0 {%k1} {z} # sched: [1:0.33]
; GENERIC-NEXT: kshiftrq $32, %k1, %k1 # sched: [1:1.00]
@@ -4659,7 +4659,7 @@ define <32 x i16> @zext_32xi1_to_32xi16(
; GENERIC: # %bb.0:
; GENERIC-NEXT: vpcmpeqw %zmm1, %zmm0, %k0 # sched: [3:1.00]
; GENERIC-NEXT: vpmovm2w %k0, %zmm0 # sched: [1:0.33]
-; GENERIC-NEXT: vpsrlw $15, %zmm0, %zmm0 # sched: [3:1.00]
+; GENERIC-NEXT: vpsrlw $15, %zmm0, %zmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: zext_32xi1_to_32xi16:
@@ -7919,7 +7919,7 @@ define void @store_32i1(<32 x i1>* %a, <
define void @store_32i1_1(<32 x i1>* %a, <32 x i16> %v) {
; GENERIC-LABEL: store_32i1_1:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: vpsllw $15, %zmm0, %zmm0 # sched: [3:1.00]
+; GENERIC-NEXT: vpsllw $15, %zmm0, %zmm0 # sched: [1:1.00]
; GENERIC-NEXT: vpmovw2m %zmm0, %k0 # sched: [1:0.33]
; GENERIC-NEXT: kmovd %k0, (%rdi) # sched: [1:1.00]
; GENERIC-NEXT: vzeroupper # sched: [100:0.33]
@@ -7942,7 +7942,7 @@ define void @store_64i1(<64 x i1>* %a, <
;
; GENERIC-LABEL: store_64i1:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: vpsllw $7, %zmm0, %zmm0 # sched: [3:1.00]
+; GENERIC-NEXT: vpsllw $7, %zmm0, %zmm0 # sched: [1:1.00]
; GENERIC-NEXT: vpmovb2m %zmm0, %k0 # sched: [1:0.33]
; GENERIC-NEXT: kmovq %k0, (%rdi) # sched: [1:1.00]
; GENERIC-NEXT: vzeroupper # sched: [100:0.33]
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