[llvm] r328617 - [PowerPC] Secure PLT support
Sterling Augustine via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 27 14:23:02 PDT 2018
[This time to everyone.]
This revision added the SecurePLT field, but missed initializing it. I have
committed r328667 to fix, as below.
Index: lib/Target/PowerPC/PPCSubtarget.cpp
===================================================================
--- lib/Target/PowerPC/PPCSubtarget.cpp (revision 328666)
+++ lib/Target/PowerPC/PPCSubtarget.cpp (revision 328667)
@@ -106,6 +106,7 @@
HasFloat128 = false;
IsISA3_0 = false;
UseLongCalls = false;
+ SecurePlt = false;
HasPOPCNTD = POPCNTD_Unavailable;
}
On Tue, Mar 27, 2018 at 11:55 AM, Galina Kistanova via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
> Hello Strahinja,
>
> This commit broke tests at one of our builders:
>
> http://lab.llvm.org:8011/builders/llvm-clang-x86_64-
> expensive-checks-win/builds/8693
>
> . . .
> Failing Tests (7):
> LLVM :: CodeGen/PowerPC/2008-10-28-f128-i32.ll
> LLVM :: CodeGen/PowerPC/big-endian-formal-args.ll
> LLVM :: CodeGen/PowerPC/calls.ll
> LLVM :: CodeGen/PowerPC/crsave.ll
> LLVM :: CodeGen/PowerPC/debuginfo-split-int.ll
> LLVM :: CodeGen/PowerPC/ppc32-pic-large.ll
> LLVM :: CodeGen/PowerPC/stack-realign.ll
>
> Please have a look?
>
> Thanks
>
> Galina
>
> On Tue, Mar 27, 2018 at 4:23 AM, Strahinja Petrovic via llvm-commits <
> llvm-commits at lists.llvm.org> wrote:
>
>> Author: spetrovic
>> Date: Tue Mar 27 04:23:53 2018
>> New Revision: 328617
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=328617&view=rev
>> Log:
>> [PowerPC] Secure PLT support
>>
>> This patch supports secure PLT mode for PowerPC 32 architecture.
>>
>> Differential Revision: https://reviews.llvm.org/D42112
>>
>> Modified:
>> llvm/trunk/lib/Target/PowerPC/PPC.td
>> llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
>> llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
>> llvm/trunk/lib/Target/PowerPC/PPCMCInstLower.cpp
>> llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h
>> llvm/trunk/test/CodeGen/PowerPC/ppc32-pic-large.ll
>>
>> Modified: llvm/trunk/lib/Target/PowerPC/PPC.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Po
>> werPC/PPC.td?rev=328617&r1=328616&r2=328617&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/PowerPC/PPC.td (original)
>> +++ llvm/trunk/lib/Target/PowerPC/PPC.td Tue Mar 27 04:23:53 2018
>> @@ -119,6 +119,8 @@ def FeatureMSYNC : SubtargetFeature<
>> [FeatureBookE]>;
>> def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true",
>> "Enable E500/E500mc
>> instructions">;
>> +def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt",
>> "true",
>> + "Enable secure plt mode">;
>> def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
>> "Enable PPC 4xx instructions">;
>> def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
>>
>> Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Po
>> werPC/PPCAsmPrinter.cpp?rev=328617&r1=328616&r2=328617&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp (original)
>> +++ llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp Tue Mar 27 04:23:53
>> 2018
>> @@ -563,33 +563,63 @@ void PPCAsmPrinter::EmitInstruction(cons
>> // Transform %rd = UpdateGBR(%rt, %ri)
>> // Into: lwz %rt, .L0$poff - .L0$pb(%ri)
>> // add %rd, %rt, %ri
>> + // or into (if secure plt mode is on):
>> + // addis r30, r30, .LTOC - .L0$pb at ha
>> + // addi r30, r30, .LTOC - .L0$pb at l
>> // Get the offset from the GOT Base Register to the GOT
>> LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
>> - MCSymbol *PICOffset =
>> - MF->getInfo<PPCFunctionInfo>()->getPICOffsetSymbol();
>> - TmpInst.setOpcode(PPC::LWZ);
>> - const MCExpr *Exp =
>> - MCSymbolRefExpr::create(PICOffset, MCSymbolRefExpr::VK_None,
>> OutContext);
>> - const MCExpr *PB =
>> - MCSymbolRefExpr::create(MF->getPICBaseSymbol(),
>> - MCSymbolRefExpr::VK_None,
>> - OutContext);
>> - const MCOperand TR = TmpInst.getOperand(1);
>> - const MCOperand PICR = TmpInst.getOperand(0);
>> + if (Subtarget->isSecurePlt() && isPositionIndependent() ) {
>> + unsigned PICR = TmpInst.getOperand(0).getReg();
>> + MCSymbol *LTOCSymbol = OutContext.getOrCreateSymbol(S
>> tringRef(".LTOC"));
>> + const MCExpr *PB =
>> + MCSymbolRefExpr::create(MF->getPICBaseSymbol(),
>> + OutContext);
>>
>> - // Step 1: lwz %rt, .L$poff - .L$pb(%ri)
>> - TmpInst.getOperand(1) =
>> - MCOperand::createExpr(MCBinaryExpr::createSub(Exp, PB,
>> OutContext));
>> - TmpInst.getOperand(0) = TR;
>> - TmpInst.getOperand(2) = PICR;
>> - EmitToStreamer(*OutStreamer, TmpInst);
>> + const MCExpr *LTOCDeltaExpr =
>> + MCBinaryExpr::createSub(MCSymbolRefExpr::create(LTOCSymbol,
>> OutContext),
>> + PB, OutContext);
>> +
>> + const MCExpr *LTOCDeltaHi =
>> + PPCMCExpr::createHa(LTOCDeltaExpr, false, OutContext);
>> + EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::ADDIS)
>> + .addReg(PICR)
>> + .addReg(PICR)
>> + .addExpr(LTOCDeltaHi));
>> +
>> + const MCExpr *LTOCDeltaLo =
>> + PPCMCExpr::createLo(LTOCDeltaExpr, false, OutContext);
>> + EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::ADDI)
>> + .addReg(PICR)
>> + .addReg(PICR)
>> + .addExpr(LTOCDeltaLo));
>> + return;
>> + } else {
>> + MCSymbol *PICOffset =
>> + MF->getInfo<PPCFunctionInfo>()->getPICOffsetSymbol();
>> + TmpInst.setOpcode(PPC::LWZ);
>> + const MCExpr *Exp =
>> + MCSymbolRefExpr::create(PICOffset, MCSymbolRefExpr::VK_None,
>> OutContext);
>> + const MCExpr *PB =
>> + MCSymbolRefExpr::create(MF->getPICBaseSymbol(),
>> + MCSymbolRefExpr::VK_None,
>> + OutContext);
>> + const MCOperand TR = TmpInst.getOperand(1);
>> + const MCOperand PICR = TmpInst.getOperand(0);
>>
>> - TmpInst.setOpcode(PPC::ADD4);
>> - TmpInst.getOperand(0) = PICR;
>> - TmpInst.getOperand(1) = TR;
>> - TmpInst.getOperand(2) = PICR;
>> - EmitToStreamer(*OutStreamer, TmpInst);
>> - return;
>> + // Step 1: lwz %rt, .L$poff - .L$pb(%ri)
>> + TmpInst.getOperand(1) =
>> + MCOperand::createExpr(MCBinaryExpr::createSub(Exp, PB,
>> OutContext));
>> + TmpInst.getOperand(0) = TR;
>> + TmpInst.getOperand(2) = PICR;
>> + EmitToStreamer(*OutStreamer, TmpInst);
>> +
>> + TmpInst.setOpcode(PPC::ADD4);
>> + TmpInst.getOperand(0) = PICR;
>> + TmpInst.getOperand(1) = TR;
>> + TmpInst.getOperand(2) = PICR;
>> + EmitToStreamer(*OutStreamer, TmpInst);
>> + return;
>> + }
>> }
>> case PPC::LWZtoc: {
>> // Transform %r3 = LWZtoc @min1, %r2
>> @@ -1233,7 +1263,7 @@ void PPCLinuxAsmPrinter::EmitFunctionEnt
>>
>> if (!Subtarget->isPPC64()) {
>> const PPCFunctionInfo *PPCFI = MF->getInfo<PPCFunctionInfo>();
>> - if (PPCFI->usesPICBase()) {
>> + if (PPCFI->usesPICBase() && !Subtarget->isSecurePlt()) {
>> MCSymbol *RelocSymbol = PPCFI->getPICOffsetSymbol();
>> MCSymbol *PICBase = MF->getPICBaseSymbol();
>> OutStreamer->EmitLabel(RelocSymbol);
>>
>> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Po
>> werPC/PPCISelDAGToDAG.cpp?rev=328617&r1=328616&r2=328617&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
>> +++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Tue Mar 27
>> 04:23:53 2018
>> @@ -4001,6 +4001,27 @@ void PPCDAGToDAGISel::Select(SDNode *N)
>> return;
>> break;
>>
>> + case PPCISD::CALL: {
>> + const Module *M = MF->getFunction().getParent();
>> +
>> + if (PPCLowering->getPointerTy(CurDAG->getDataLayout()) != MVT::i32
>> ||
>> + !PPCSubTarget->isSecurePlt() || !PPCSubTarget->isTargetELF() ||
>> + M->getPICLevel() == PICLevel::SmallPIC)
>> + break;
>> +
>> + SDValue Op = N->getOperand(1);
>> +
>> + if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) {
>> + if (GA->getTargetFlags() == PPCII::MO_PLT)
>> + getGlobalBaseReg();
>> + }
>> + else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op))
>> {
>> + if (ES->getTargetFlags() == PPCII::MO_PLT)
>> + getGlobalBaseReg();
>> + }
>> + }
>> + break;
>> +
>> case PPCISD::GlobalBaseReg:
>> ReplaceNode(N, getGlobalBaseReg());
>> return;
>>
>> Modified: llvm/trunk/lib/Target/PowerPC/PPCMCInstLower.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Po
>> werPC/PPCMCInstLower.cpp?rev=328617&r1=328616&r2=328617&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/PowerPC/PPCMCInstLower.cpp (original)
>> +++ llvm/trunk/lib/Target/PowerPC/PPCMCInstLower.cpp Tue Mar 27 04:23:53
>> 2018
>> @@ -107,10 +107,20 @@ static MCOperand GetSymbolRef(const Mach
>> break;
>> }
>>
>> - if (MO.getTargetFlags() == PPCII::MO_PLT)
>> + if (MO.getTargetFlags() == PPCII::MO_PLT)
>> RefKind = MCSymbolRefExpr::VK_PLT;
>>
>> + const MachineFunction *MF = MO.getParent()->getParent()->getParent();
>> + const PPCSubtarget *Subtarget = &(MF->getSubtarget<PPCSubtarget>());
>> + const TargetMachine &TM = Printer.TM;
>> const MCExpr *Expr = MCSymbolRefExpr::create(Symbol, RefKind, Ctx);
>> + // -msecure-plt option works only in PIC mode. If secure plt mode
>> + // is on add 32768 to symbol.
>> + if (Subtarget->isSecurePlt() && TM.isPositionIndependent() &&
>> + MO.getTargetFlags() == PPCII::MO_PLT)
>> + Expr = MCBinaryExpr::createAdd(Expr,
>> + MCConstantExpr::create(32768, Ctx),
>> + Ctx);
>>
>> if (!MO.isJTI() && MO.getOffset())
>> Expr = MCBinaryExpr::createAdd(Expr,
>>
>> Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Po
>> werPC/PPCSubtarget.h?rev=328617&r1=328616&r2=328617&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h (original)
>> +++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h Tue Mar 27 04:23:53 2018
>> @@ -133,6 +133,7 @@ protected:
>> bool HasFloat128;
>> bool IsISA3_0;
>> bool UseLongCalls;
>> + bool SecurePlt;
>>
>> POPCNTDKind HasPOPCNTD;
>>
>> @@ -255,6 +256,7 @@ public:
>> bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
>> bool isPPC4xx() const { return IsPPC4xx; }
>> bool isPPC6xx() const { return IsPPC6xx; }
>> + bool isSecurePlt() const {return SecurePlt; }
>> bool isE500() const { return IsE500; }
>> bool isFeatureMFTB() const { return FeatureMFTB; }
>> bool isDeprecatedDST() const { return DeprecatedDST; }
>>
>> Modified: llvm/trunk/test/CodeGen/PowerPC/ppc32-pic-large.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/
>> PowerPC/ppc32-pic-large.ll?rev=328617&r1=328616&r2=328617&view=diff
>> ============================================================
>> ==================
>> --- llvm/trunk/test/CodeGen/PowerPC/ppc32-pic-large.ll (original)
>> +++ llvm/trunk/test/CodeGen/PowerPC/ppc32-pic-large.ll Tue Mar 27
>> 04:23:53 2018
>> @@ -1,4 +1,5 @@
>> ; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu
>> -relocation-model=pic | FileCheck -check-prefix=LARGE-BSS %s
>> +; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -mattr=+secure-plt
>> -relocation-model=pic | FileCheck -check-prefix=LARGE-SECUREPLT %s
>> @bar = common global i32 0, align 4
>>
>> declare i32 @call_foo(i32, ...)
>> @@ -29,3 +30,6 @@ entry:
>> ; LARGE-BSS: [[VREF]]:
>> ; LARGE-BSS-NEXT: .p2align 2
>> ; LARGE-BSS-NEXT: .long bar
>> +; LARGE-SECUREPLT: addis 30, 30, .LTOC-.L0$pb at ha
>> +; LARGE-SECUREPLT: addi 30, 30, .LTOC-.L0$pb at l
>> +; LARGE-SECUREPLT: bl call_foo at PLT+32768
>>
>>
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