[llvm] r328192 - [X86] Use the default AES scheduler classes directly. NFCI.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 22 06:18:08 PDT 2018
Author: rksimon
Date: Thu Mar 22 06:18:08 2018
New Revision: 328192
URL: http://llvm.org/viewvc/llvm-project?rev=328192&view=rev
Log:
[X86] Use the default AES scheduler classes directly. NFCI.
Models were completely overriding all AES instructions when the WriteAES default classes could be used for exactly the same coverage.
Removes 6 unnecessary scheduler classes from every model.
Note: Still looking for a way for tblgen to warn when this is happening - often the override is more complete than the default.
Modified:
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=328192&r1=328191&r2=328192&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Thu Mar 22 06:18:08 2018
@@ -211,27 +211,35 @@ def : WriteRes<WritePCmpEStrILd, [BWPort
// AES instructions.
def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption.
let Latency = 7;
+ let NumMicroOps = 1;
let ResourceCycles = [1];
}
def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> {
- let Latency = 7;
- let ResourceCycles = [1, 1];
+ let Latency = 12;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
}
+
def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn.
let Latency = 14;
+ let NumMicroOps = 2;
let ResourceCycles = [2];
}
def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> {
- let Latency = 14;
- let ResourceCycles = [2, 1];
+ let Latency = 19;
+ let NumMicroOps = 3;
+ let ResourceCycles = [2,1];
}
-def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5]> { // Key Generation.
- let Latency = 10;
- let ResourceCycles = [2, 8];
+
+def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5, BWPort015]> { // Key Generation.
+ let Latency = 29;
+ let NumMicroOps = 11;
+ let ResourceCycles = [2,7,2];
}
-def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23]> {
- let Latency = 10;
- let ResourceCycles = [2, 7, 1];
+def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> {
+ let Latency = 33;
+ let NumMicroOps = 11;
+ let ResourceCycles = [2,7,1,1];
}
// Carry-less multiplication instructions.
@@ -2148,20 +2156,6 @@ def BWWriteResGroup71 : SchedWriteRes<[B
}
def: InstRW<[BWWriteResGroup71], (instregex "STD")>;
-def BWWriteResGroup72 : SchedWriteRes<[BWPort5]> {
- let Latency = 7;
- let NumMicroOps = 1;
- let ResourceCycles = [1];
-}
-def: InstRW<[BWWriteResGroup72], (instregex "AESDECLASTrr",
- "AESDECrr",
- "AESENCLASTrr",
- "AESENCrr",
- "VAESDECLASTrr",
- "VAESDECrr",
- "VAESENCLASTrr",
- "VAESENCrr")>;
-
def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> {
let Latency = 7;
let NumMicroOps = 2;
@@ -3021,20 +3015,6 @@ def BWWriteResGroup133 : SchedWriteRes<[
def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>;
def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>;
-def BWWriteResGroup134 : SchedWriteRes<[BWPort5,BWPort23]> {
- let Latency = 12;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[BWWriteResGroup134], (instregex "AESDECLASTrm",
- "AESDECrm",
- "AESENCLASTrm",
- "AESENCrm",
- "VAESDECLASTrm",
- "VAESDECrm",
- "VAESENCLASTrm",
- "VAESENCrm")>;
-
def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> {
let Latency = 12;
let NumMicroOps = 3;
@@ -3083,13 +3063,6 @@ def: InstRW<[BWWriteResGroup139], (instr
"VSQRTPSr",
"VSQRTSSr")>;
-def BWWriteResGroup140 : SchedWriteRes<[BWPort5]> {
- let Latency = 14;
- let NumMicroOps = 2;
- let ResourceCycles = [2];
-}
-def: InstRW<[BWWriteResGroup140], (instregex "(V?)AESIMCrr")>;
-
def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
let Latency = 14;
let NumMicroOps = 3;
@@ -3252,13 +3225,6 @@ def: InstRW<[BWWriteResGroup161], (instr
"VSQRTPSm",
"VSQRTSSm")>;
-def BWWriteResGroup162 : SchedWriteRes<[BWPort5,BWPort23]> {
- let Latency = 19;
- let NumMicroOps = 3;
- let ResourceCycles = [2,1];
-}
-def: InstRW<[BWWriteResGroup162], (instregex "(V?)AESIMCrm")>;
-
def BWWriteResGroup163 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
let Latency = 19;
let NumMicroOps = 5;
@@ -3470,13 +3436,6 @@ def BWWriteResGroup183_7 : SchedWriteRes
}
def: InstRW<[BWWriteResGroup183_7], (instrs VGATHERQPSrm)>;
-def BWWriteResGroup184 : SchedWriteRes<[BWPort0,BWPort5,BWPort015]> {
- let Latency = 29;
- let NumMicroOps = 11;
- let ResourceCycles = [2,7,2];
-}
-def: InstRW<[BWWriteResGroup184], (instregex "(V?)AESKEYGENASSIST128rr")>;
-
def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
let Latency = 29;
let NumMicroOps = 27;
@@ -3498,13 +3457,6 @@ def BWWriteResGroup187 : SchedWriteRes<[
}
def: InstRW<[BWWriteResGroup187], (instregex "MMX_EMMS")>;
-def BWWriteResGroup188 : SchedWriteRes<[BWPort0,BWPort5,BWPort23,BWPort015]> {
- let Latency = 33;
- let NumMicroOps = 11;
- let ResourceCycles = [2,7,1,1];
-}
-def: InstRW<[BWWriteResGroup188], (instregex "(V?)AESKEYGENASSIST128rm")>;
-
def BWWriteResGroup189 : SchedWriteRes<[BWPort0,BWPort015]> {
let Latency = 34;
let NumMicroOps = 3;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=328192&r1=328191&r2=328192&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Thu Mar 22 06:18:08 2018
@@ -210,29 +210,35 @@ def : WriteRes<WritePCmpEStrILd, [HWPort
// AES Instructions.
def : WriteRes<WriteAESDecEnc, [HWPort5]> {
let Latency = 7;
+ let NumMicroOps = 1;
let ResourceCycles = [1];
}
def : WriteRes<WriteAESDecEncLd, [HWPort5, HWPort23]> {
- let Latency = 7;
- let ResourceCycles = [1, 1];
+ let Latency = 13;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
}
def : WriteRes<WriteAESIMC, [HWPort5]> {
let Latency = 14;
+ let NumMicroOps = 2;
let ResourceCycles = [2];
}
def : WriteRes<WriteAESIMCLd, [HWPort5, HWPort23]> {
- let Latency = 14;
- let ResourceCycles = [2, 1];
+ let Latency = 20;
+ let NumMicroOps = 3;
+ let ResourceCycles = [2,1];
}
-def : WriteRes<WriteAESKeyGen, [HWPort0, HWPort5]> {
- let Latency = 10;
- let ResourceCycles = [2, 8];
+def : WriteRes<WriteAESKeyGen, [HWPort0,HWPort5,HWPort015]> {
+ let Latency = 29;
+ let NumMicroOps = 11;
+ let ResourceCycles = [2,7,2];
}
-def : WriteRes<WriteAESKeyGenLd, [HWPort0, HWPort5, HWPort23]> {
- let Latency = 10;
- let ResourceCycles = [2, 7, 1];
+def : WriteRes<WriteAESKeyGenLd, [HWPort0,HWPort5,HWPort23,HWPort015]> {
+ let Latency = 34;
+ let NumMicroOps = 11;
+ let ResourceCycles = [2,7,1,1];
}
// Carry-less multiplication instructions.
@@ -2833,26 +2839,6 @@ def HWWriteResGroup109 : SchedWriteRes<[
def: InstRW<[HWWriteResGroup109], (instregex "SHLD(16|32|64)mrCL",
"SHRD(16|32|64)mrCL")>;
-def HWWriteResGroup110 : SchedWriteRes<[HWPort5]> {
- let Latency = 7;
- let NumMicroOps = 1;
- let ResourceCycles = [1];
-}
-def: InstRW<[HWWriteResGroup110], (instregex "VAESDECLASTrr",
- "VAESDECrr",
- "VAESENCLASTrr",
- "VAESENCrr")>;
-
-def HWWriteResGroup111 : SchedWriteRes<[HWPort5,HWPort23]> {
- let Latency = 13;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[HWWriteResGroup111], (instregex "(V?)AESDECLASTrm",
- "(V?)AESDECrm",
- "(V?)AESENCLASTrm",
- "(V?)AESENCrm")>;
-
def HWWriteResGroup112 : SchedWriteRes<[HWPort0,HWPort5]> {
let Latency = 7;
let NumMicroOps = 3;
@@ -3065,13 +3051,6 @@ def: InstRW<[HWWriteResGroup136], (instr
"VSQRTPSr",
"VSQRTSSr")>;
-def HWWriteResGroup137 : SchedWriteRes<[HWPort5]> {
- let Latency = 14;
- let NumMicroOps = 2;
- let ResourceCycles = [2];
-}
-def: InstRW<[HWWriteResGroup137], (instregex "(V?)AESIMCrr")>;
-
def HWWriteResGroup138 : SchedWriteRes<[HWPort0,HWPort23]> {
let Latency = 20;
let NumMicroOps = 2;
@@ -3080,13 +3059,6 @@ def HWWriteResGroup138 : SchedWriteRes<[
def: InstRW<[HWWriteResGroup138], (instregex "DIVPDrm",
"VSQRTPSm")>;
-def HWWriteResGroup139 : SchedWriteRes<[HWPort5,HWPort23]> {
- let Latency = 20;
- let NumMicroOps = 3;
- let ResourceCycles = [2,1];
-}
-def: InstRW<[HWWriteResGroup139], (instregex "(V?)AESIMCrm")>;
-
def HWWriteResGroup140 : SchedWriteRes<[HWPort0,HWPort1,HWPort5]> {
let Latency = 14;
let NumMicroOps = 4;
@@ -3312,20 +3284,6 @@ def HWWriteResGroup166 : SchedWriteRes<[
def: InstRW<[HWWriteResGroup166], (instregex "DIV_FI16m",
"DIV_FI32m")>;
-def HWWriteResGroup167 : SchedWriteRes<[HWPort0,HWPort5,HWPort23,HWPort015]> {
- let Latency = 34;
- let NumMicroOps = 11;
- let ResourceCycles = [2,7,1,1];
-}
-def: InstRW<[HWWriteResGroup167], (instregex "(V?)AESKEYGENASSIST128rm")>;
-
-def HWWriteResGroup168 : SchedWriteRes<[HWPort0,HWPort5,HWPort015]> {
- let Latency = 29;
- let NumMicroOps = 11;
- let ResourceCycles = [2,7,2];
-}
-def: InstRW<[HWWriteResGroup168], (instregex "(V?)AESKEYGENASSIST128rr")>;
-
def HWWriteResGroup170 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort06,HWPort0156]> {
let Latency = 35;
let NumMicroOps = 23;
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=328192&r1=328191&r2=328192&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Thu Mar 22 06:18:08 2018
@@ -1266,16 +1266,6 @@ def: InstRW<[SBWriteResGroup56], (instre
"(V?)XORPDrm",
"(V?)XORPSrm")>;
-def SBWriteResGroup57 : SchedWriteRes<[SBPort5,SBPort015]> {
- let Latency = 7;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SBWriteResGroup57], (instregex "(V?)AESDECLASTrr",
- "(V?)AESDECrr",
- "(V?)AESENCLASTrr",
- "(V?)AESENCrr")>;
-
def SBWriteResGroup58 : SchedWriteRes<[SBPort23,SBPort05]> {
let Latency = 7;
let NumMicroOps = 2;
@@ -1962,13 +1952,6 @@ def: InstRW<[SBWriteResGroup109], (instr
"(V?)HSUBPDrm",
"(V?)HSUBPSrm")>;
-def SBWriteResGroup110 : SchedWriteRes<[SBPort5]> {
- let Latency = 12;
- let NumMicroOps = 2;
- let ResourceCycles = [2];
-}
-def: InstRW<[SBWriteResGroup110], (instregex "(V?)AESIMCrr")>;
-
def SBWriteResGroup111 : SchedWriteRes<[SBPort0,SBPort23]> {
let Latency = 12;
let NumMicroOps = 2;
@@ -2009,16 +1992,6 @@ def: InstRW<[SBWriteResGroup114], (instr
"SUB_FI16m",
"SUB_FI32m")>;
-def SBWriteResGroup115 : SchedWriteRes<[SBPort5,SBPort23,SBPort015]> {
- let Latency = 13;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[SBWriteResGroup115], (instregex "(V?)AESDECLASTrm",
- "(V?)AESDECrm",
- "(V?)AESENCLASTrm",
- "(V?)AESENCrm")>;
-
def SBWriteResGroup116 : SchedWriteRes<[SBPort0]> {
let Latency = 14;
let NumMicroOps = 1;
@@ -2067,13 +2040,6 @@ def SBWriteResGroup121 : SchedWriteRes<[
def: InstRW<[SBWriteResGroup121], (instregex "(V?)PCMPISTRIrm",
"(V?)PCMPISTRM128rm")>;
-def SBWriteResGroup122 : SchedWriteRes<[SBPort5,SBPort23]> {
- let Latency = 18;
- let NumMicroOps = 3;
- let ResourceCycles = [2,1];
-}
-def: InstRW<[SBWriteResGroup122], (instregex "(V?)AESIMCrm")>;
-
def SBWriteResGroup123 : SchedWriteRes<[SBPort0,SBPort23]> {
let Latency = 20;
let NumMicroOps = 2;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=328192&r1=328191&r2=328192&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Thu Mar 22 06:18:08 2018
@@ -212,29 +212,37 @@ def : WriteRes<WritePCmpEStrILd, [SKLPor
}
// AES instructions.
-def : WriteRes<WriteAESDecEnc, [SKLPort5]> { // Decryption, encryption.
- let Latency = 7;
+def : WriteRes<WriteAESDecEnc, [SKLPort0]> { // Decryption, encryption.
+ let Latency = 4;
+ let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def : WriteRes<WriteAESDecEncLd, [SKLPort5, SKLPort23]> {
- let Latency = 7;
- let ResourceCycles = [1, 1];
+def : WriteRes<WriteAESDecEncLd, [SKLPort0, SKLPort23]> {
+ let Latency = 10;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
}
-def : WriteRes<WriteAESIMC, [SKLPort5]> { // InvMixColumn.
- let Latency = 14;
+
+def : WriteRes<WriteAESIMC, [SKLPort0]> { // InvMixColumn.
+ let Latency = 8;
+ let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def : WriteRes<WriteAESIMCLd, [SKLPort5, SKLPort23]> {
+def : WriteRes<WriteAESIMCLd, [SKLPort0, SKLPort23]> {
let Latency = 14;
- let ResourceCycles = [2, 1];
+ let NumMicroOps = 3;
+ let ResourceCycles = [2,1];
}
-def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5]> { // Key Generation.
- let Latency = 10;
- let ResourceCycles = [2, 8];
+
+def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5, SKLPort015]> { // Key Generation.
+ let Latency = 20;
+ let NumMicroOps = 11;
+ let ResourceCycles = [3,6,2];
}
-def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23]> {
- let Latency = 10;
- let ResourceCycles = [2, 7, 1];
+def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23, SKLPort015]> {
+ let Latency = 25;
+ let NumMicroOps = 11;
+ let ResourceCycles = [3,6,1,1];
}
// Carry-less multiplication instructions.
@@ -1371,11 +1379,7 @@ def SKLWriteResGroup47 : SchedWriteRes<[
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup47], (instregex "AESDECLASTrr",
- "AESDECrr",
- "AESENCLASTrr",
- "AESENCrr",
- "MMX_PMADDUBSWrr",
+def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMADDUBSWrr",
"MMX_PMADDWDirr",
"MMX_PMULHRSWrr",
"MMX_PMULHUWirr",
@@ -1389,10 +1393,6 @@ def: InstRW<[SKLWriteResGroup47], (instr
"RCPSSr",
"RSQRTPSr",
"RSQRTSSr",
- "VAESDECLASTrr",
- "VAESDECrr",
- "VAESENCLASTrr",
- "VAESENCrr",
"VRCPPSYr",
"VRCPPSr",
"VRCPSSr",
@@ -2394,13 +2394,6 @@ def SKLWriteResGroup103 : SchedWriteRes<
}
def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>;
-def SKLWriteResGroup104 : SchedWriteRes<[SKLPort0]> {
- let Latency = 8;
- let NumMicroOps = 2;
- let ResourceCycles = [2];
-}
-def: InstRW<[SKLWriteResGroup104], (instregex "(V?)AESIMCrr")>;
-
def SKLWriteResGroup105 : SchedWriteRes<[SKLPort015]> {
let Latency = 8;
let NumMicroOps = 2;
@@ -2828,11 +2821,7 @@ def SKLWriteResGroup132 : SchedWriteRes<
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup132], (instregex "(V?)AESDECLASTrm",
- "(V?)AESDECrm",
- "(V?)AESENCLASTrm",
- "(V?)AESENCrm",
- "(V?)RCPPSm",
+def: InstRW<[SKLWriteResGroup132], (instregex "(V?)RCPPSm",
"(V?)RSQRTPSm")>;
def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> {
@@ -3232,13 +3221,6 @@ def: InstRW<[SKLWriteResGroup166], (inst
"VDIVPDrr",
"VDIVSDrr")>;
-def SKLWriteResGroup167 : SchedWriteRes<[SKLPort0,SKLPort23]> {
- let Latency = 14;
- let NumMicroOps = 3;
- let ResourceCycles = [2,1];
-}
-def: InstRW<[SKLWriteResGroup167], (instregex "(V?)AESIMCrm")>;
-
def SKLWriteResGroup168 : SchedWriteRes<[SKLPort23,SKLPort015]> {
let Latency = 14;
let NumMicroOps = 3;
@@ -3457,13 +3439,6 @@ def SKLWriteResGroup193 : SchedWriteRes<
}
def: InstRW<[SKLWriteResGroup193], (instregex "MWAITrr")>;
-def SKLWriteResGroup194 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort015]> {
- let Latency = 20;
- let NumMicroOps = 11;
- let ResourceCycles = [3,6,2];
-}
-def: InstRW<[SKLWriteResGroup194], (instregex "(V?)AESKEYGENASSIST128rr")>;
-
def SKLWriteResGroup195 : SchedWriteRes<[SKLPort0,SKLPort23]> {
let Latency = 21;
let NumMicroOps = 2;
@@ -3558,13 +3533,6 @@ def SKLWriteResGroup203 : SchedWriteRes<
}
def: InstRW<[SKLWriteResGroup203], (instregex "(V?)PCMPESTRM128rm")>;
-def SKLWriteResGroup204 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort015]> {
- let Latency = 25;
- let NumMicroOps = 11;
- let ResourceCycles = [3,6,1,1];
-}
-def: InstRW<[SKLWriteResGroup204], (instregex "(V?)AESKEYGENASSIST128rm")>;
-
def SKLWriteResGroup205 : SchedWriteRes<[SKLPort0,SKLPort23]> {
let Latency = 26;
let NumMicroOps = 2;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=328192&r1=328191&r2=328192&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Thu Mar 22 06:18:08 2018
@@ -212,29 +212,37 @@ def : WriteRes<WritePCmpEStrILd, [SKXPor
}
// AES instructions.
-def : WriteRes<WriteAESDecEnc, [SKXPort5]> { // Decryption, encryption.
- let Latency = 7;
+def : WriteRes<WriteAESDecEnc, [SKXPort0]> { // Decryption, encryption.
+ let Latency = 4;
+ let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def : WriteRes<WriteAESDecEncLd, [SKXPort5, SKXPort23]> {
- let Latency = 7;
- let ResourceCycles = [1, 1];
+def : WriteRes<WriteAESDecEncLd, [SKXPort0, SKXPort23]> {
+ let Latency = 10;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
}
-def : WriteRes<WriteAESIMC, [SKXPort5]> { // InvMixColumn.
- let Latency = 14;
+
+def : WriteRes<WriteAESIMC, [SKXPort0]> { // InvMixColumn.
+ let Latency = 8;
+ let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def : WriteRes<WriteAESIMCLd, [SKXPort5, SKXPort23]> {
+def : WriteRes<WriteAESIMCLd, [SKXPort0, SKXPort23]> {
let Latency = 14;
- let ResourceCycles = [2, 1];
+ let NumMicroOps = 3;
+ let ResourceCycles = [2,1];
}
-def : WriteRes<WriteAESKeyGen, [SKXPort0, SKXPort5]> { // Key Generation.
- let Latency = 10;
- let ResourceCycles = [2, 8];
+
+def : WriteRes<WriteAESKeyGen, [SKXPort0,SKXPort5,SKXPort015]> { // Key Generation.
+ let Latency = 20;
+ let NumMicroOps = 11;
+ let ResourceCycles = [3,6,2];
}
-def : WriteRes<WriteAESKeyGenLd, [SKXPort0, SKXPort5, SKXPort23]> {
- let Latency = 10;
- let ResourceCycles = [2, 7, 1];
+def : WriteRes<WriteAESKeyGenLd, [SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {
+ let Latency = 25;
+ let NumMicroOps = 11;
+ let ResourceCycles = [3,6,1,1];
}
// Carry-less multiplication instructions.
@@ -2179,11 +2187,7 @@ def SKXWriteResGroup49 : SchedWriteRes<[
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKXWriteResGroup49], (instregex "AESDECLASTrr",
- "AESDECrr",
- "AESENCLASTrr",
- "AESENCrr",
- "MMX_PMADDUBSWrr",
+def: InstRW<[SKXWriteResGroup49], (instregex "MMX_PMADDUBSWrr",
"MMX_PMADDWDirr",
"MMX_PMULHRSWrr",
"MMX_PMULHUWirr",
@@ -2197,10 +2201,6 @@ def: InstRW<[SKXWriteResGroup49], (instr
"RCPSSr",
"RSQRTPSr",
"RSQRTSSr",
- "VAESDECLASTrr",
- "VAESDECrr",
- "VAESENCLASTrr",
- "VAESENCrr",
"VRCP14PDZ128r(b?)(k?)(z?)",
"VRCP14PDZ256r(b?)(k?)(z?)",
"VRCP14PSZ128r(b?)(k?)(z?)",
@@ -3852,13 +3852,6 @@ def SKXWriteResGroup114 : SchedWriteRes<
}
def: InstRW<[SKXWriteResGroup114], (instrs VSCATTERDPSZmr)>;
-def SKXWriteResGroup115 : SchedWriteRes<[SKXPort0]> {
- let Latency = 8;
- let NumMicroOps = 2;
- let ResourceCycles = [2];
-}
-def: InstRW<[SKXWriteResGroup115], (instregex "(V?)AESIMCrr")>;
-
def SKXWriteResGroup116 : SchedWriteRes<[SKXPort015]> {
let Latency = 8;
let NumMicroOps = 2;
@@ -4702,16 +4695,8 @@ def SKXWriteResGroup147 : SchedWriteRes<
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKXWriteResGroup147], (instregex "AESDECLASTrm",
- "AESDECrm",
- "AESENCLASTrm",
- "AESENCrm",
- "RCPPSm",
+def: InstRW<[SKXWriteResGroup147], (instregex "RCPPSm",
"RSQRTPSm",
- "VAESDECLASTrm",
- "VAESDECrm",
- "VAESENCLASTrm",
- "VAESENCrm",
"VRCP14PDZ128m(b?)(k?)(z?)",
"VRCP14PSZ128m(b?)(k?)(z?)",
"VRCP14SDrm(b?)(k?)(z?)",
@@ -5509,13 +5494,6 @@ def: InstRW<[SKXWriteResGroup184], (inst
"VDIVSDZrr(b?)(_Int)?(k?)(z?)",
"VDIVSDrr")>;
-def SKXWriteResGroup185 : SchedWriteRes<[SKXPort0,SKXPort23]> {
- let Latency = 14;
- let NumMicroOps = 3;
- let ResourceCycles = [2,1];
-}
-def: InstRW<[SKXWriteResGroup185], (instregex "(V?)AESIMCrm")>;
-
def SKXWriteResGroup186 : SchedWriteRes<[SKXPort23,SKXPort015]> {
let Latency = 14;
let NumMicroOps = 3;
@@ -5844,13 +5822,6 @@ def SKXWriteResGroup220 : SchedWriteRes<
}
def: InstRW<[SKXWriteResGroup220], (instregex "MWAITrr")>;
-def SKXWriteResGroup221 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort015]> {
- let Latency = 20;
- let NumMicroOps = 11;
- let ResourceCycles = [3,6,2];
-}
-def: InstRW<[SKXWriteResGroup221], (instregex "(V?)AESKEYGENASSIST128rr")>;
-
def SKXWriteResGroup222 : SchedWriteRes<[SKXPort0,SKXPort23]> {
let Latency = 21;
let NumMicroOps = 2;
@@ -6007,13 +5978,6 @@ def SKXWriteResGroup235 : SchedWriteRes<
}
def: InstRW<[SKXWriteResGroup235], (instregex "(V?)PCMPESTRM128rm")>;
-def SKXWriteResGroup236 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {
- let Latency = 25;
- let NumMicroOps = 11;
- let ResourceCycles = [3,6,1,1];
-}
-def: InstRW<[SKXWriteResGroup236], (instregex "(V?)AESKEYGENASSIST128rm")>;
-
def SKXWriteResGroup237 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> {
let Latency = 26;
let NumMicroOps = 4;
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