[llvm] r320404 - [Hexagon] Add support for Hexagon V65
Eric Christopher via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 20 11:44:51 PDT 2018
For the record you really should have broken this up into separate commits.
69 files changed, 13364 insertions(+), 5905 deletions(-)
-eric
On Mon, Dec 11, 2017 at 10:58 AM Krzysztof Parzyszek via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
> Author: kparzysz
> Date: Mon Dec 11 10:57:54 2017
> New Revision: 320404
>
> URL: http://llvm.org/viewvc/llvm-project?rev=320404&view=rev
> Log:
> [Hexagon] Add support for Hexagon V65
>
> Added:
> llvm/trunk/lib/Target/Hexagon/HexagonDepDecoders.h
> llvm/trunk/lib/Target/Hexagon/HexagonGatherPacketize.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV65.td
> llvm/trunk/lib/Target/Hexagon/HexagonMapAsm2IntrinV65.gen.td
> llvm/trunk/lib/Target/Hexagon/HexagonPatternsV65.td
> llvm/trunk/lib/Target/Hexagon/HexagonScheduleV65.td
> llvm/trunk/test/CodeGen/Hexagon/intrinsics/v65-gather-double.ll
> llvm/trunk/test/CodeGen/Hexagon/intrinsics/v65-gather.ll
> llvm/trunk/test/CodeGen/Hexagon/intrinsics/v65-scatter-double.ll
> llvm/trunk/test/CodeGen/Hexagon/intrinsics/v65-scatter-gather.ll
> llvm/trunk/test/CodeGen/Hexagon/intrinsics/v65-scatter.ll
> llvm/trunk/test/CodeGen/Hexagon/intrinsics/v65.ll
> llvm/trunk/test/MC/Hexagon/hvx-double-implies-hvx.s
> llvm/trunk/test/MC/Hexagon/v65_all.s
> llvm/trunk/test/MC/Hexagon/vpred_defs.s
> llvm/trunk/test/MC/Hexagon/vscatter-slot.s
> llvm/trunk/test/MC/Hexagon/vtmp_def.s
> Modified:
> llvm/trunk/include/llvm/BinaryFormat/ELF.h
> llvm/trunk/include/llvm/IR/IntrinsicsHexagon.td
> llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
> llvm/trunk/lib/Target/Hexagon/CMakeLists.txt
> llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
> llvm/trunk/lib/Target/Hexagon/Hexagon.td
> llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonDepArch.h
> llvm/trunk/lib/Target/Hexagon/HexagonDepArch.td
> llvm/trunk/lib/Target/Hexagon/HexagonDepIICHVX.td
> llvm/trunk/lib/Target/Hexagon/HexagonDepIICScalar.td
> llvm/trunk/lib/Target/Hexagon/HexagonDepITypes.h
> llvm/trunk/lib/Target/Hexagon/HexagonDepITypes.td
> llvm/trunk/lib/Target/Hexagon/HexagonDepInstrFormats.td
> llvm/trunk/lib/Target/Hexagon/HexagonDepInstrInfo.td
> llvm/trunk/lib/Target/Hexagon/HexagonDepMappings.td
> llvm/trunk/lib/Target/Hexagon/HexagonDepOperands.td
> llvm/trunk/lib/Target/Hexagon/HexagonDepTimingClasses.h
> llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonIICHVX.td
> llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.h
> llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
> llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td
> llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h
> llvm/trunk/lib/Target/Hexagon/HexagonIntrinsics.td
> llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td
> llvm/trunk/lib/Target/Hexagon/HexagonSchedule.td
> llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h
> llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.h
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h
> llvm/trunk/test/CodeGen/Hexagon/livephysregs-lane-masks.mir
> llvm/trunk/test/MC/Hexagon/PacketRules/endloop_branches.s
> llvm/trunk/test/MC/Hexagon/new-value-check.s
> llvm/trunk/test/MC/Hexagon/v60-misc.s
>
> Modified: llvm/trunk/include/llvm/BinaryFormat/ELF.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/BinaryFormat/ELF.h?rev=320404&r1=320403&r2=320404&view=diff
>
> ==============================================================================
> --- llvm/trunk/include/llvm/BinaryFormat/ELF.h (original)
> +++ llvm/trunk/include/llvm/BinaryFormat/ELF.h Mon Dec 11 10:57:54 2017
> @@ -584,6 +584,7 @@ enum {
> EF_HEXAGON_MACH_V55 = 0x00000005, // Hexagon V55
> EF_HEXAGON_MACH_V60 = 0x00000060, // Hexagon V60
> EF_HEXAGON_MACH_V62 = 0x00000062, // Hexagon V62
> + EF_HEXAGON_MACH_V65 = 0x00000065, // Hexagon V65
>
> // Highest ISA version flags
> EF_HEXAGON_ISA_MACH = 0x00000000, // Same as specified in bits[11:0]
> @@ -595,6 +596,7 @@ enum {
> EF_HEXAGON_ISA_V55 = 0x00000050, // Hexagon V55 ISA
> EF_HEXAGON_ISA_V60 = 0x00000060, // Hexagon V60 ISA
> EF_HEXAGON_ISA_V62 = 0x00000062, // Hexagon V62 ISA
> + EF_HEXAGON_ISA_V65 = 0x00000065, // Hexagon V65 ISA
> };
>
> // Hexagon-specific section indexes for common small data
>
> Modified: llvm/trunk/include/llvm/IR/IntrinsicsHexagon.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsHexagon.td?rev=320404&r1=320403&r2=320404&view=diff
>
> ==============================================================================
> --- llvm/trunk/include/llvm/IR/IntrinsicsHexagon.td (original)
> +++ llvm/trunk/include/llvm/IR/IntrinsicsHexagon.td Mon Dec 11 10:57:54
> 2017
> @@ -5044,7 +5044,6 @@ def int_hexagon_V6_vassignp_128B :
> Hexagon_v2048v2048_Intrinsic_T<"HEXAGON_V6_vassignp_128B">;
>
>
> -
> //
> // Hexagon_iii_Intrinsic<string GCCIntSuffix>
> // tag : S6_rol_i_r
> @@ -5583,54 +5582,6 @@ class Hexagon_v1024i_Intrinsic<string GC
> [IntrNoMem]>;
>
> //
> -// Hexagon_v512v512LLii_Intrinsic<string GCCIntSuffix>
> -// tag : V6_vlutb
> -class Hexagon_v512v512LLii_Intrinsic<string GCCIntSuffix>
> - : Hexagon_Intrinsic<GCCIntSuffix,
> - [llvm_v16i32_ty],
> [llvm_v16i32_ty,llvm_i64_ty,llvm_i32_ty],
> - [IntrNoMem]>;
> -
> -//
> -// Hexagon_v1024v1024LLii_Intrinsic<string GCCIntSuffix>
> -// tag : V6_vlutb_128B
> -class Hexagon_v1024v1024LLii_Intrinsic<string GCCIntSuffix>
> - : Hexagon_Intrinsic<GCCIntSuffix,
> - [llvm_v32i32_ty],
> [llvm_v32i32_ty,llvm_i64_ty,llvm_i32_ty],
> - [IntrNoMem]>;
> -
> -//
> -// Hexagon_v512v512v512LLii_Intrinsic<string GCCIntSuffix>
> -// tag : V6_vlutb_acc
> -class Hexagon_v512v512v512LLii_Intrinsic<string GCCIntSuffix>
> - : Hexagon_Intrinsic<GCCIntSuffix,
> - [llvm_v16i32_ty],
> [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i64_ty,llvm_i32_ty],
> - [IntrNoMem]>;
> -
> -//
> -// Hexagon_v1024v1024v1024LLii_Intrinsic<string GCCIntSuffix>
> -// tag : V6_vlutb_acc_128B
> -class Hexagon_v1024v1024v1024LLii_Intrinsic<string GCCIntSuffix>
> - : Hexagon_Intrinsic<GCCIntSuffix,
> - [llvm_v32i32_ty],
> [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i64_ty,llvm_i32_ty],
> - [IntrNoMem]>;
> -
> -//
> -// Hexagon_v2048v2048LLii_Intrinsic<string GCCIntSuffix>
> -// tag : V6_vlutb_dv_128B
> -class Hexagon_v2048v2048LLii_Intrinsic<string GCCIntSuffix>
> - : Hexagon_Intrinsic<GCCIntSuffix,
> - [llvm_v64i32_ty],
> [llvm_v64i32_ty,llvm_i64_ty,llvm_i32_ty],
> - [IntrNoMem]>;
> -
> -//
> -// Hexagon_v2048v2048v2048LLii_Intrinsic<string GCCIntSuffix>
> -// tag : V6_vlutb_dv_acc_128B
> -class Hexagon_v2048v2048v2048LLii_Intrinsic<string GCCIntSuffix>
> - : Hexagon_Intrinsic<GCCIntSuffix,
> - [llvm_v64i32_ty],
> [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i64_ty,llvm_i32_ty],
> - [IntrNoMem]>;
> -
> -//
> // Hexagon_v512v512v512v512i_Intrinsic<string GCCIntSuffix>
> // tag : V6_vlutvvb_oracc
> class Hexagon_v512v512v512v512i_Intrinsic<string GCCIntSuffix>
> @@ -9167,54 +9118,6 @@ def int_hexagon_V6_vcombine_128B :
> Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vcombine_128B">;
>
> //
> -// BUILTIN_INFO(HEXAGON.V6_vlutb,VI_ftype_VIDISI,3)
> -// tag : V6_vlutb
> -def int_hexagon_V6_vlutb :
> -Hexagon_v512v512LLii_Intrinsic<"HEXAGON_V6_vlutb">;
> -
> -//
> -// BUILTIN_INFO(HEXAGON.V6_vlutb_128B,VI_ftype_VIDISI,3)
> -// tag : V6_vlutb_128B
> -def int_hexagon_V6_vlutb_128B :
> -Hexagon_v1024v1024LLii_Intrinsic<"HEXAGON_V6_vlutb_128B">;
> -
> -//
> -// BUILTIN_INFO(HEXAGON.V6_vlutb_acc,VI_ftype_VIVIDISI,4)
> -// tag : V6_vlutb_acc
> -def int_hexagon_V6_vlutb_acc :
> -Hexagon_v512v512v512LLii_Intrinsic<"HEXAGON_V6_vlutb_acc">;
> -
> -//
> -// BUILTIN_INFO(HEXAGON.V6_vlutb_acc_128B,VI_ftype_VIVIDISI,4)
> -// tag : V6_vlutb_acc_128B
> -def int_hexagon_V6_vlutb_acc_128B :
> -Hexagon_v1024v1024v1024LLii_Intrinsic<"HEXAGON_V6_vlutb_acc_128B">;
> -
> -//
> -// BUILTIN_INFO(HEXAGON.V6_vlutb_dv,VD_ftype_VDDISI,3)
> -// tag : V6_vlutb_dv
> -def int_hexagon_V6_vlutb_dv :
> -Hexagon_v1024v1024LLii_Intrinsic<"HEXAGON_V6_vlutb_dv">;
> -
> -//
> -// BUILTIN_INFO(HEXAGON.V6_vlutb_dv_128B,VD_ftype_VDDISI,3)
> -// tag : V6_vlutb_dv_128B
> -def int_hexagon_V6_vlutb_dv_128B :
> -Hexagon_v2048v2048LLii_Intrinsic<"HEXAGON_V6_vlutb_dv_128B">;
> -
> -//
> -// BUILTIN_INFO(HEXAGON.V6_vlutb_dv_acc,VD_ftype_VDVDDISI,4)
> -// tag : V6_vlutb_dv_acc
> -def int_hexagon_V6_vlutb_dv_acc :
> -Hexagon_v1024v1024v1024LLii_Intrinsic<"HEXAGON_V6_vlutb_dv_acc">;
> -
> -//
> -// BUILTIN_INFO(HEXAGON.V6_vlutb_dv_acc_128B,VD_ftype_VDVDDISI,4)
> -// tag : V6_vlutb_dv_acc_128B
> -def int_hexagon_V6_vlutb_dv_acc_128B :
> -Hexagon_v2048v2048v2048LLii_Intrinsic<"HEXAGON_V6_vlutb_dv_acc_128B">;
> -
> -//
> // BUILTIN_INFO(HEXAGON.V6_vdelta,VI_ftype_VIVI,2)
> // tag : V6_vdelta
> def int_hexagon_V6_vdelta :
> @@ -9349,6 +9252,30 @@ Hexagon_v2048v2048v1024v1024i_Intrinsic<
> //
> // Masked vector stores
> //
> +def int_hexagon_V6_vS32b_qpred_ai :
> +Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai">;
> +
> +def int_hexagon_V6_vS32b_nqpred_ai :
> +Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai">;
> +
> +def int_hexagon_V6_vS32b_nt_qpred_ai :
> +Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai">;
> +
> +def int_hexagon_V6_vS32b_nt_nqpred_ai :
> +Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai">;
> +
> +def int_hexagon_V6_vS32b_qpred_ai_128B :
> +Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai_128B">;
> +
> +def int_hexagon_V6_vS32b_nqpred_ai_128B :
> +Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai_128B">;
> +
> +def int_hexagon_V6_vS32b_nt_qpred_ai_128B :
> +Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai_128B">;
> +
> +def int_hexagon_V6_vS32b_nt_nqpred_ai_128B :
> +Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai_128B">;
> +
> def int_hexagon_V6_vmaskedstoreq :
> Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstoreq">;
>
> @@ -9642,6 +9569,20 @@ class Hexagon_V62_v2048v2048v1024v1024i_
> [llvm_v64i32_ty],
> [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
> [IntrNoMem]>;
>
> +// Hexagon_v512v64iv512v512v64i_Intrinsic<string GCCIntSuffix>
> +// tag: V6_vaddcarry
> +class Hexagon_v512v64iv512v512v64i_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_v16i32_ty, llvm_v512i1_ty],
> [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v512i1_ty],
> + [IntrNoMem]>;
> +
> +// Hexagon_v1024v128iv1024v1024v128i_Intrinsic<string GCCIntSuffix>
> +// tag: V6_vaddcarry_128B
> +class Hexagon_v1024v128iv1024v1024v128i_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_v32i32_ty, llvm_v1024i1_ty],
> [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v1024i1_ty],
> + [IntrNoMem]>;
> +
>
> //
> // BUILTIN_INFO(HEXAGON.M6_vabsdiffb,DI_ftype_DIDI,2)
> @@ -10213,3 +10154,821 @@ Hexagon_V62_v1024v512v512i_Intrinsic<"HE
> def int_hexagon_V6_vlutvwh_nm_128B :
> Hexagon_V62_v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvwh_nm_128B">;
>
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vaddcarry,VI_ftype_VIVIQV,3)
> +// tag: V6_vaddcarry
> +def int_hexagon_V6_vaddcarry :
> +Hexagon_v512v64iv512v512v64i_Intrinsic<"HEXAGON_v6_vaddcarry">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vaddcarry_128B,VI_ftype_VIVIQV,3)
> +// tag: V6_vaddcarry_128B
> +def int_hexagon_V6_vaddcarry_128B :
> +Hexagon_v1024v128iv1024v1024v128i_Intrinsic<"HEXAGON_v6_vaddcarry_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vsubcarry,VI_ftype_VIVIQV,3)
> +// tag: V6_vsubcarry
> +def int_hexagon_V6_vsubcarry :
> +Hexagon_v512v64iv512v512v64i_Intrinsic<"HEXAGON_v6_vsubcarry">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vsubcarry_128B,VI_ftype_VIVIQV,3)
> +// tag: V6_vsubcarry_128B
> +def int_hexagon_V6_vsubcarry_128B :
> +Hexagon_v1024v128iv1024v1024v128i_Intrinsic<"HEXAGON_v6_vsubcarry_128B">;
> +
> +
> +///
> +/// HexagonV65 intrinsics
> +///
> +
> +//
> +// Hexagon_V65_iLLiLLi_Intrinsic<string GCCIntSuffix>
> +// tag : A6_vcmpbeq_notany
> +class Hexagon_V65_iLLiLLi_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty],
> + [IntrNoMem]>;
> +
> +//
> +// Hexagon_V65_v1024v512LLi_Intrinsic<string GCCIntSuffix>
> +// tag : V6_vrmpyub_rtt
> +class Hexagon_V65_v1024v512LLi_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i64_ty],
> + [IntrNoMem]>;
> +
> +//
> +// Hexagon_V65_v2048v1024LLi_Intrinsic<string GCCIntSuffix>
> +// tag : V6_vrmpyub_rtt_128B
> +class Hexagon_V65_v2048v1024LLi_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i64_ty],
> + [IntrNoMem]>;
> +
> +//
> +// Hexagon_V65_v1024v1024v512LLi_Intrinsic<string GCCIntSuffix>
> +// tag : V6_vrmpyub_rtt_acc
> +class Hexagon_V65_v1024v1024v512LLi_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_v32i32_ty],
> [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i64_ty],
> + [IntrNoMem]>;
> +
> +//
> +// Hexagon_V65_v2048v2048v1024LLi_Intrinsic<string GCCIntSuffix>
> +// tag : V6_vrmpyub_rtt_acc_128B
> +class Hexagon_V65_v2048v2048v1024LLi_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_v64i32_ty],
> [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i64_ty],
> + [IntrNoMem]>;
> +
> +//
> +// Hexagon_V65_v512v512v512i_Intrinsic<string GCCIntSuffix>
> +// tag : V6_vasruwuhsat
> +class Hexagon_V65_v512v512v512i_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_v16i32_ty],
> [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
> + [IntrNoMem]>;
> +
> +//
> +// Hexagon_V65_v1024v1024v1024i_Intrinsic<string GCCIntSuffix>
> +// tag : V6_vasruwuhsat_128B
> +class Hexagon_V65_v1024v1024v1024i_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_v32i32_ty],
> [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
> + [IntrNoMem]>;
> +
> +//
> +// Hexagon_V65_v512v512v512_Intrinsic<string GCCIntSuffix>
> +// tag : V6_vavguw
> +class Hexagon_V65_v512v512v512_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_v16i32_ty],
> [llvm_v16i32_ty,llvm_v16i32_ty],
> + [IntrNoMem]>;
> +
> +//
> +// Hexagon_V65_v1024v1024v1024_Intrinsic<string GCCIntSuffix>
> +// tag : V6_vavguw_128B
> +class Hexagon_V65_v1024v1024v1024_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_v32i32_ty],
> [llvm_v32i32_ty,llvm_v32i32_ty],
> + [IntrNoMem]>;
> +
> +//
> +// Hexagon_V65_v512v512_Intrinsic<string GCCIntSuffix>
> +// tag : V6_vabsb
> +class Hexagon_V65_v512v512_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_v16i32_ty], [llvm_v16i32_ty],
> + [IntrNoMem]>;
> +
> +//
> +// Hexagon_V65_v1024v1024_Intrinsic<string GCCIntSuffix>
> +// tag : V6_vabsb_128B
> +class Hexagon_V65_v1024v1024_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_v32i32_ty], [llvm_v32i32_ty],
> + [IntrNoMem]>;
> +
> +//
> +// Hexagon_V65_v1024v1024i_Intrinsic<string GCCIntSuffix>
> +// tag : V6_vmpabuu
> +class Hexagon_V65_v1024v1024i_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
> + [IntrNoMem]>;
> +
> +//
> +// Hexagon_V65_v2048v2048i_Intrinsic<string GCCIntSuffix>
> +// tag : V6_vmpabuu_128B
> +class Hexagon_V65_v2048v2048i_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty],
> + [IntrNoMem]>;
> +
> +//
> +// Hexagon_V65_v2048v2048v2048i_Intrinsic<string GCCIntSuffix>
> +// tag : V6_vmpabuu_acc_128B
> +class Hexagon_V65_v2048v2048v2048i_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_v64i32_ty],
> [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty],
> + [IntrNoMem]>;
> +
> +//
> +// Hexagon_V65_v1024v1024v512i_Intrinsic<string GCCIntSuffix>
> +// tag : V6_vmpyh_acc
> +class Hexagon_V65_v1024v1024v512i_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_v32i32_ty],
> [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i32_ty],
> + [IntrNoMem]>;
> +
> +//
> +// Hexagon_V65_v2048v2048v1024i_Intrinsic<string GCCIntSuffix>
> +// tag : V6_vmpyh_acc_128B
> +class Hexagon_V65_v2048v2048v1024i_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_v64i32_ty],
> [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i32_ty],
> + [IntrNoMem]>;
> +
> +//
> +// Hexagon_V65_v512v512v512LLi_Intrinsic<string GCCIntSuffix>
> +// tag : V6_vmpahhsat
> +class Hexagon_V65_v512v512v512LLi_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_v16i32_ty],
> [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i64_ty],
> + [IntrNoMem]>;
> +
> +//
> +// Hexagon_V65_v1024v1024v1024LLi_Intrinsic<string GCCIntSuffix>
> +// tag : V6_vmpahhsat_128B
> +class Hexagon_V65_v1024v1024v1024LLi_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_v32i32_ty],
> [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i64_ty],
> + [IntrNoMem]>;
> +
> +//
> +// Hexagon_V65_v512v512LLi_Intrinsic<string GCCIntSuffix>
> +// tag : V6_vlut4
> +class Hexagon_V65_v512v512LLi_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i64_ty],
> + [IntrNoMem]>;
> +
> +//
> +// Hexagon_V65_v1024v1024LLi_Intrinsic<string GCCIntSuffix>
> +// tag : V6_vlut4_128B
> +class Hexagon_V65_v1024v1024LLi_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i64_ty],
> + [IntrNoMem]>;
> +
> +//
> +// Hexagon_V65_v512v512i_Intrinsic<string GCCIntSuffix>
> +// tag : V6_vmpyuhe
> +class Hexagon_V65_v512v512i_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i32_ty],
> + [IntrNoMem]>;
> +
> +//
> +// Hexagon_V65_v512v64i_Intrinsic<string GCCIntSuffix>
> +// tag : V6_vprefixqb
> +class Hexagon_V65_v512v64i_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_v16i32_ty], [llvm_v512i1_ty],
> + [IntrNoMem]>;
> +
> +//
> +// Hexagon_V65_v1024v128i_Intrinsic<string GCCIntSuffix>
> +// tag : V6_vprefixqb_128B
> +class Hexagon_V65_v1024v128i_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_v32i32_ty], [llvm_v1024i1_ty],
> + [IntrNoMem]>;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.A6_vcmpbeq_notany,QI_ftype_DIDI,2)
> +// tag : A6_vcmpbeq_notany
> +def int_hexagon_A6_vcmpbeq_notany :
> +Hexagon_V65_iLLiLLi_Intrinsic<"HEXAGON_A6_vcmpbeq_notany">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.A6_vcmpbeq_notany_128B,QI_ftype_DIDI,2)
> +// tag : A6_vcmpbeq_notany_128B
> +def int_hexagon_A6_vcmpbeq_notany_128B :
> +Hexagon_V65_iLLiLLi_Intrinsic<"HEXAGON_A6_vcmpbeq_notany_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt,VD_ftype_VIDI,2)
> +// tag : V6_vrmpyub_rtt
> +def int_hexagon_V6_vrmpyub_rtt :
> +Hexagon_V65_v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt_128B,VD_ftype_VIDI,2)
> +// tag : V6_vrmpyub_rtt_128B
> +def int_hexagon_V6_vrmpyub_rtt_128B :
> +Hexagon_V65_v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt_acc,VD_ftype_VDVIDI,3)
> +// tag : V6_vrmpyub_rtt_acc
> +def int_hexagon_V6_vrmpyub_rtt_acc :
> +Hexagon_V65_v1024v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt_acc_128B,VD_ftype_VDVIDI,3)
> +// tag : V6_vrmpyub_rtt_acc_128B
> +def int_hexagon_V6_vrmpyub_rtt_acc_128B :
>
> +Hexagon_V65_v2048v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt,VD_ftype_VIDI,2)
> +// tag : V6_vrmpybub_rtt
> +def int_hexagon_V6_vrmpybub_rtt :
> +Hexagon_V65_v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt_128B,VD_ftype_VIDI,2)
> +// tag : V6_vrmpybub_rtt_128B
> +def int_hexagon_V6_vrmpybub_rtt_128B :
> +Hexagon_V65_v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt_acc,VD_ftype_VDVIDI,3)
> +// tag : V6_vrmpybub_rtt_acc
> +def int_hexagon_V6_vrmpybub_rtt_acc :
> +Hexagon_V65_v1024v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt_acc_128B,VD_ftype_VDVIDI,3)
> +// tag : V6_vrmpybub_rtt_acc_128B
> +def int_hexagon_V6_vrmpybub_rtt_acc_128B :
>
> +Hexagon_V65_v2048v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vasruwuhsat,VI_ftype_VIVISI,3)
> +// tag : V6_vasruwuhsat
> +def int_hexagon_V6_vasruwuhsat :
> +Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasruwuhsat">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vasruwuhsat_128B,VI_ftype_VIVISI,3)
> +// tag : V6_vasruwuhsat_128B
> +def int_hexagon_V6_vasruwuhsat_128B :
> +Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasruwuhsat_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vasruhubsat,VI_ftype_VIVISI,3)
> +// tag : V6_vasruhubsat
> +def int_hexagon_V6_vasruhubsat :
> +Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasruhubsat">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vasruhubsat_128B,VI_ftype_VIVISI,3)
> +// tag : V6_vasruhubsat_128B
> +def int_hexagon_V6_vasruhubsat_128B :
> +Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasruhubsat_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vasruhubrndsat,VI_ftype_VIVISI,3)
> +// tag : V6_vasruhubrndsat
> +def int_hexagon_V6_vasruhubrndsat :
> +Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasruhubrndsat">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vasruhubrndsat_128B,VI_ftype_VIVISI,3)
> +// tag : V6_vasruhubrndsat_128B
> +def int_hexagon_V6_vasruhubrndsat_128B :
> +Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasruhubrndsat_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vaslh_acc,VI_ftype_VIVISI,3)
> +// tag : V6_vaslh_acc
> +def int_hexagon_V6_vaslh_acc :
> +Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vaslh_acc">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vaslh_acc_128B,VI_ftype_VIVISI,3)
> +// tag : V6_vaslh_acc_128B
> +def int_hexagon_V6_vaslh_acc_128B :
> +Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vaslh_acc_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vasrh_acc,VI_ftype_VIVISI,3)
> +// tag : V6_vasrh_acc
> +def int_hexagon_V6_vasrh_acc :
> +Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrh_acc">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vasrh_acc_128B,VI_ftype_VIVISI,3)
> +// tag : V6_vasrh_acc_128B
> +def int_hexagon_V6_vasrh_acc_128B :
> +Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrh_acc_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vavguw,VI_ftype_VIVI,2)
> +// tag : V6_vavguw
> +def int_hexagon_V6_vavguw :
> +Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavguw">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vavguw_128B,VI_ftype_VIVI,2)
> +// tag : V6_vavguw_128B
> +def int_hexagon_V6_vavguw_128B :
> +Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavguw_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vavguwrnd,VI_ftype_VIVI,2)
> +// tag : V6_vavguwrnd
> +def int_hexagon_V6_vavguwrnd :
> +Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavguwrnd">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vavguwrnd_128B,VI_ftype_VIVI,2)
> +// tag : V6_vavguwrnd_128B
> +def int_hexagon_V6_vavguwrnd_128B :
> +Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavguwrnd_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vavgb,VI_ftype_VIVI,2)
> +// tag : V6_vavgb
> +def int_hexagon_V6_vavgb :
> +Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavgb">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vavgb_128B,VI_ftype_VIVI,2)
> +// tag : V6_vavgb_128B
> +def int_hexagon_V6_vavgb_128B :
> +Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgb_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vavgbrnd,VI_ftype_VIVI,2)
> +// tag : V6_vavgbrnd
> +def int_hexagon_V6_vavgbrnd :
> +Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavgbrnd">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vavgbrnd_128B,VI_ftype_VIVI,2)
> +// tag : V6_vavgbrnd_128B
> +def int_hexagon_V6_vavgbrnd_128B :
> +Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgbrnd_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vnavgb,VI_ftype_VIVI,2)
> +// tag : V6_vnavgb
> +def int_hexagon_V6_vnavgb :
> +Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vnavgb">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vnavgb_128B,VI_ftype_VIVI,2)
> +// tag : V6_vnavgb_128B
> +def int_hexagon_V6_vnavgb_128B :
> +Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vnavgb_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vabsb,VI_ftype_VI,1)
> +// tag : V6_vabsb
> +def int_hexagon_V6_vabsb :
> +Hexagon_V65_v512v512_Intrinsic<"HEXAGON_V6_vabsb">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vabsb_128B,VI_ftype_VI,1)
> +// tag : V6_vabsb_128B
> +def int_hexagon_V6_vabsb_128B :
> +Hexagon_V65_v1024v1024_Intrinsic<"HEXAGON_V6_vabsb_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vabsb_sat,VI_ftype_VI,1)
> +// tag : V6_vabsb_sat
> +def int_hexagon_V6_vabsb_sat :
> +Hexagon_V65_v512v512_Intrinsic<"HEXAGON_V6_vabsb_sat">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vabsb_sat_128B,VI_ftype_VI,1)
> +// tag : V6_vabsb_sat_128B
> +def int_hexagon_V6_vabsb_sat_128B :
> +Hexagon_V65_v1024v1024_Intrinsic<"HEXAGON_V6_vabsb_sat_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vmpabuu,VD_ftype_VDSI,2)
> +// tag : V6_vmpabuu
> +def int_hexagon_V6_vmpabuu :
> +Hexagon_V65_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpabuu">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vmpabuu_128B,VD_ftype_VDSI,2)
> +// tag : V6_vmpabuu_128B
> +def int_hexagon_V6_vmpabuu_128B :
> +Hexagon_V65_v2048v2048i_Intrinsic<"HEXAGON_V6_vmpabuu_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vmpabuu_acc,VD_ftype_VDVDSI,3)
> +// tag : V6_vmpabuu_acc
> +def int_hexagon_V6_vmpabuu_acc :
> +Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpabuu_acc">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vmpabuu_acc_128B,VD_ftype_VDVDSI,3)
> +// tag : V6_vmpabuu_acc_128B
> +def int_hexagon_V6_vmpabuu_acc_128B :
> +Hexagon_V65_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vmpabuu_acc_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vmpyh_acc,VD_ftype_VDVISI,3)
> +// tag : V6_vmpyh_acc
> +def int_hexagon_V6_vmpyh_acc :
> +Hexagon_V65_v1024v1024v512i_Intrinsic<"HEXAGON_V6_vmpyh_acc">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vmpyh_acc_128B,VD_ftype_VDVISI,3)
> +// tag : V6_vmpyh_acc_128B
> +def int_hexagon_V6_vmpyh_acc_128B :
> +Hexagon_V65_v2048v2048v1024i_Intrinsic<"HEXAGON_V6_vmpyh_acc_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vmpahhsat,VI_ftype_VIVIDI,3)
> +// tag : V6_vmpahhsat
> +def int_hexagon_V6_vmpahhsat :
> +Hexagon_V65_v512v512v512LLi_Intrinsic<"HEXAGON_V6_vmpahhsat">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vmpahhsat_128B,VI_ftype_VIVIDI,3)
> +// tag : V6_vmpahhsat_128B
> +def int_hexagon_V6_vmpahhsat_128B :
> +Hexagon_V65_v1024v1024v1024LLi_Intrinsic<"HEXAGON_V6_vmpahhsat_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vmpauhuhsat,VI_ftype_VIVIDI,3)
> +// tag : V6_vmpauhuhsat
> +def int_hexagon_V6_vmpauhuhsat :
> +Hexagon_V65_v512v512v512LLi_Intrinsic<"HEXAGON_V6_vmpauhuhsat">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vmpauhuhsat_128B,VI_ftype_VIVIDI,3)
> +// tag : V6_vmpauhuhsat_128B
> +def int_hexagon_V6_vmpauhuhsat_128B :
> +Hexagon_V65_v1024v1024v1024LLi_Intrinsic<"HEXAGON_V6_vmpauhuhsat_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vmpsuhuhsat,VI_ftype_VIVIDI,3)
> +// tag : V6_vmpsuhuhsat
> +def int_hexagon_V6_vmpsuhuhsat :
> +Hexagon_V65_v512v512v512LLi_Intrinsic<"HEXAGON_V6_vmpsuhuhsat">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vmpsuhuhsat_128B,VI_ftype_VIVIDI,3)
> +// tag : V6_vmpsuhuhsat_128B
> +def int_hexagon_V6_vmpsuhuhsat_128B :
> +Hexagon_V65_v1024v1024v1024LLi_Intrinsic<"HEXAGON_V6_vmpsuhuhsat_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vlut4,VI_ftype_VIDI,2)
> +// tag : V6_vlut4
> +def int_hexagon_V6_vlut4 :
> +Hexagon_V65_v512v512LLi_Intrinsic<"HEXAGON_V6_vlut4">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vlut4_128B,VI_ftype_VIDI,2)
> +// tag : V6_vlut4_128B
> +def int_hexagon_V6_vlut4_128B :
> +Hexagon_V65_v1024v1024LLi_Intrinsic<"HEXAGON_V6_vlut4_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vmpyuhe,VI_ftype_VISI,2)
> +// tag : V6_vmpyuhe
> +def int_hexagon_V6_vmpyuhe :
> +Hexagon_V65_v512v512i_Intrinsic<"HEXAGON_V6_vmpyuhe">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vmpyuhe_128B,VI_ftype_VISI,2)
> +// tag : V6_vmpyuhe_128B
> +def int_hexagon_V6_vmpyuhe_128B :
> +Hexagon_V65_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyuhe_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vmpyuhe_acc,VI_ftype_VIVISI,3)
> +// tag : V6_vmpyuhe_acc
> +def int_hexagon_V6_vmpyuhe_acc :
> +Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vmpyuhe_acc">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vmpyuhe_acc_128B,VI_ftype_VIVISI,3)
> +// tag : V6_vmpyuhe_acc_128B
> +def int_hexagon_V6_vmpyuhe_acc_128B :
> +Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyuhe_acc_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vprefixqb,VI_ftype_QV,1)
> +// tag : V6_vprefixqb
> +def int_hexagon_V6_vprefixqb :
> +Hexagon_V65_v512v64i_Intrinsic<"HEXAGON_V6_vprefixqb">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vprefixqb_128B,VI_ftype_QV,1)
> +// tag : V6_vprefixqb_128B
> +def int_hexagon_V6_vprefixqb_128B :
> +Hexagon_V65_v1024v128i_Intrinsic<"HEXAGON_V6_vprefixqb_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vprefixqh,VI_ftype_QV,1)
> +// tag : V6_vprefixqh
> +def int_hexagon_V6_vprefixqh :
> +Hexagon_V65_v512v64i_Intrinsic<"HEXAGON_V6_vprefixqh">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vprefixqh_128B,VI_ftype_QV,1)
> +// tag : V6_vprefixqh_128B
> +def int_hexagon_V6_vprefixqh_128B :
> +Hexagon_V65_v1024v128i_Intrinsic<"HEXAGON_V6_vprefixqh_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vprefixqw,VI_ftype_QV,1)
> +// tag : V6_vprefixqw
> +def int_hexagon_V6_vprefixqw :
> +Hexagon_V65_v512v64i_Intrinsic<"HEXAGON_V6_vprefixqw">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vprefixqw_128B,VI_ftype_QV,1)
> +// tag : V6_vprefixqw_128B
> +def int_hexagon_V6_vprefixqw_128B :
> +Hexagon_V65_v1024v128i_Intrinsic<"HEXAGON_V6_vprefixqw_128B">;
> +
> +
> +// The scatter/gather ones below will not be generated from iset.py. Make
> sure
> +// you don't overwrite these.
> +class Hexagon_V65_vvmemiiv512_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,
> + llvm_v16i32_ty],
> + [IntrArgMemOnly]>;
> +
> +class Hexagon_V65_vvmemiiv1024_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,
> + llvm_v32i32_ty],
> + [IntrArgMemOnly]>;
> +
> +class Hexagon_V65_vvmemiiv2048_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,
> + llvm_v64i32_ty],
> + [IntrArgMemOnly]>;
> +
> +class Hexagon_V65_vvmemv64iiiv512_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty,
> + llvm_i32_ty,llvm_v16i32_ty],
> + [IntrArgMemOnly]>;
> +
> +class Hexagon_V65_vvmemv128iiiv1024_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty,
> + llvm_i32_ty,llvm_v32i32_ty],
> + [IntrArgMemOnly]>;
> +
> +class Hexagon_V65_vvmemv64iiiv1024_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty,
> + llvm_i32_ty,llvm_v32i32_ty],
> + [IntrArgMemOnly]>;
> +
> +class Hexagon_V65_vvmemv128iiiv2048_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty,
> + llvm_i32_ty,llvm_v64i32_ty],
> + [IntrArgMemOnly]>;
> +
> +def int_hexagon_V6_vgathermw :
> +Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermw">;
> +
> +def int_hexagon_V6_vgathermw_128B :
> +Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermw_128B">;
> +
> +def int_hexagon_V6_vgathermh :
> +Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermh">;
> +
> +def int_hexagon_V6_vgathermh_128B :
> +Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermh_128B">;
> +
> +def int_hexagon_V6_vgathermhw :
> +Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermhw">;
> +
> +def int_hexagon_V6_vgathermhw_128B :
> +Hexagon_V65_vvmemiiv2048_Intrinsic<"HEXAGON_V6_vgathermhw_128B">;
> +
> +def int_hexagon_V6_vgathermwq :
> +Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermwq">;
> +
> +def int_hexagon_V6_vgathermwq_128B :
> +Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermwq_128B">;
> +
> +def int_hexagon_V6_vgathermhq :
> +Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermhq">;
> +
> +def int_hexagon_V6_vgathermhq_128B :
> +Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhq_128B">;
> +
> +def int_hexagon_V6_vgathermhwq :
> +Hexagon_V65_vvmemv64iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhwq">;
> +
> +def int_hexagon_V6_vgathermhwq_128B :
> +Hexagon_V65_vvmemv128iiiv2048_Intrinsic<"HEXAGON_V6_vgathermhwq_128B">;
> +
> +class Hexagon_V65_viiv512v512_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [], [llvm_i32_ty,llvm_i32_ty,
> + llvm_v16i32_ty,llvm_v16i32_ty],
> + [IntrWriteMem]>;
> +
> +class Hexagon_V65_viiv1024v1024_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [], [llvm_i32_ty,llvm_i32_ty,
> + llvm_v32i32_ty,llvm_v32i32_ty],
> + [IntrWriteMem]>;
> +
> +class Hexagon_V65_vv64iiiv512v512_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [], [llvm_v512i1_ty,llvm_i32_ty,
> + llvm_i32_ty,llvm_v16i32_ty,
> + llvm_v16i32_ty],
> + [IntrWriteMem]>;
> +
> +class Hexagon_V65_vv128iiiv1024v1024_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [], [llvm_v1024i1_ty,llvm_i32_ty,
> + llvm_i32_ty,llvm_v32i32_ty,
> + llvm_v32i32_ty],
> + [IntrWriteMem]>;
> +
> +class Hexagon_V65_viiv1024v512_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [], [llvm_i32_ty,llvm_i32_ty,
> + llvm_v32i32_ty,llvm_v16i32_ty],
> + [IntrWriteMem]>;
> +
> +class Hexagon_V65_viiv2048v1024_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [], [llvm_i32_ty,llvm_i32_ty,
> + llvm_v64i32_ty,llvm_v32i32_ty],
> + [IntrWriteMem]>;
> +
> +class Hexagon_V65_vv64iiiv1024v512_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [], [llvm_v512i1_ty,llvm_i32_ty,
> + llvm_i32_ty,llvm_v32i32_ty,
> + llvm_v16i32_ty],
> + [IntrWriteMem]>;
> +
> +class Hexagon_V65_vv128iiiv2048v1024_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [], [llvm_v1024i1_ty,llvm_i32_ty,
> + llvm_i32_ty,llvm_v64i32_ty,
> + llvm_v32i32_ty],
> + [IntrWriteMem]>;
> +
> +class Hexagon_V65_v2048_Intrinsic<string GCCIntSuffix>
> + : Hexagon_Intrinsic<GCCIntSuffix,
> + [llvm_v64i32_ty], [],
> + [IntrNoMem]>;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vscattermw,v_ftype_SISIVIVI,4)
> +// tag : V6_vscattermw
> +def int_hexagon_V6_vscattermw :
> +Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vscattermw_128B,v_ftype_SISIVIVI,4)
> +// tag : V6_vscattermw_128B
> +def int_hexagon_V6_vscattermw_128B :
> +Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vscattermh,v_ftype_SISIVIVI,4)
> +// tag : V6_vscattermh
> +def int_hexagon_V6_vscattermh :
> +Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vscattermh_128B,v_ftype_SISIVIVI,4)
> +// tag : V6_vscattermh_128B
> +def int_hexagon_V6_vscattermh_128B :
> +Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vscattermw_add,v_ftype_SISIVIVI,4)
> +// tag : V6_vscattermw_add
> +def int_hexagon_V6_vscattermw_add :
> +Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw_add">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vscattermw_add_128B,v_ftype_SISIVIVI,4)
> +// tag : V6_vscattermw_add_128B
> +def int_hexagon_V6_vscattermw_add_128B :
> +Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_add_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vscattermh_add,v_ftype_SISIVIVI,4)
> +// tag : V6_vscattermh_add
> +def int_hexagon_V6_vscattermh_add :
> +Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh_add">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vscattermh_add_128B,v_ftype_SISIVIVI,4)
> +// tag : V6_vscattermh_add_128B
> +def int_hexagon_V6_vscattermh_add_128B :
> +Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_add_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vscattermwq,v_ftype_QVSISIVIVI,5)
> +// tag : V6_vscattermwq
> +def int_hexagon_V6_vscattermwq :
> +Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermwq">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vscattermwq_128B,v_ftype_QVSISIVIVI,5)
> +// tag : V6_vscattermwq_128B
> +def int_hexagon_V6_vscattermwq_128B :
> +Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermwq_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vscattermhq,v_ftype_QVSISIVIVI,5)
> +// tag : V6_vscattermhq
> +def int_hexagon_V6_vscattermhq :
> +Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermhq">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vscattermhq_128B,v_ftype_QVSISIVIVI,5)
> +// tag : V6_vscattermhq_128B
> +def int_hexagon_V6_vscattermhq_128B :
> +Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermhq_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vscattermhw,v_ftype_SISIVDVI,4)
> +// tag : V6_vscattermhw
> +def int_hexagon_V6_vscattermhw :
> +Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vscattermhw_128B,v_ftype_SISIVDVI,4)
> +// tag : V6_vscattermhw_128B
> +def int_hexagon_V6_vscattermhw_128B :
> +Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vscattermhwq,v_ftype_QVSISIVDVI,5)
> +// tag : V6_vscattermhwq
> +def int_hexagon_V6_vscattermhwq :
> +Hexagon_V65_vv64iiiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhwq">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vscattermhwq_128B,v_ftype_QVSISIVDVI,5)
> +// tag : V6_vscattermhwq_128B
> +def int_hexagon_V6_vscattermhwq_128B :
> +Hexagon_V65_vv128iiiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhwq_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vscattermhw_add,v_ftype_SISIVDVI,4)
> +// tag : V6_vscattermhw_add
> +def int_hexagon_V6_vscattermhw_add :
> +Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw_add">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vscattermhw_add_128B,v_ftype_SISIVDVI,4)
> +// tag : V6_vscattermhw_add_128B
> +def int_hexagon_V6_vscattermhw_add_128B :
> +Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_add_128B">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vdd0,VD_ftype_,0)
> +// tag : V6_vdd0
> +def int_hexagon_V6_vdd0 :
> +Hexagon_v1024_Intrinsic<"HEXAGON_V6_vdd0">;
> +
> +//
> +// BUILTIN_INFO(HEXAGON.V6_vdd0_128B,VD_ftype_,0)
> +// tag : V6_vdd0_128B
> +def int_hexagon_V6_vdd0_128B :
> +Hexagon_V65_v2048_Intrinsic<"HEXAGON_V6_vdd0_128B">;
>
> Modified: llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp?rev=320404&r1=320403&r2=320404&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp (original)
> +++ llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp Mon Dec
> 11 10:57:54 2017
> @@ -47,6 +47,7 @@
> #include "llvm/Support/Format.h"
> #include "llvm/Support/MathExtras.h"
> #include "llvm/Support/SMLoc.h"
> +#include "llvm/Support/SourceMgr.h"
> #include "llvm/Support/TargetRegistry.h"
> #include "llvm/Support/raw_ostream.h"
> #include <algorithm>
> @@ -60,9 +61,6 @@
>
> using namespace llvm;
>
> -static cl::opt<bool> EnableFutureRegs("mfuture-regs",
> - cl::desc("Enable future
> registers"));
> -
> static cl::opt<bool> WarnMissingParenthesis(
> "mwarn-missing-parenthesis",
> cl::desc("Warn for missing parenthesis around predicate registers"),
> @@ -95,12 +93,20 @@ class HexagonAsmParser : public MCTarget
> }
>
> MCAsmParser &Parser;
> - MCAssembler *Assembler;
> MCInst MCB;
> bool InBrackets;
>
> MCAsmParser &getParser() const { return Parser; }
> - MCAssembler *getAssembler() const { return Assembler; }
> + MCAssembler *getAssembler() const {
> + MCAssembler *Assembler = nullptr;
> + // FIXME: need better way to detect AsmStreamer (upstream removed
> getKind())
> + if (!Parser.getStreamer().hasRawTextSupport()) {
> + MCELFStreamer *MES = static_cast<MCELFStreamer
> *>(&Parser.getStreamer());
> + Assembler = &MES->getAssembler();
> + }
> + return Assembler;
> + }
> +
> MCAsmLexer &getLexer() const { return Parser.getLexer(); }
>
> bool equalIsAsmAssignment() override { return false; }
> @@ -123,7 +129,7 @@ class HexagonAsmParser : public MCTarget
> bool matchOneInstruction(MCInst &MCB, SMLoc IDLoc,
> OperandVector &InstOperands, uint64_t
> &ErrorInfo,
> bool MatchingInlineAsm);
> -
> + void eatToEndOfPacket();
> bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
> OperandVector &Operands, MCStreamer &Out,
> uint64_t &ErrorInfo,
> @@ -155,17 +161,11 @@ public:
> HexagonAsmParser(const MCSubtargetInfo &_STI, MCAsmParser &_Parser,
> const MCInstrInfo &MII, const MCTargetOptions &Options)
> : MCTargetAsmParser(Options, _STI, MII), Parser(_Parser),
> - MCB(HexagonMCInstrInfo::createBundle()), InBrackets(false) {
> + InBrackets(false) {
> + MCB.setOpcode(Hexagon::BUNDLE);
>
> setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
>
> MCAsmParserExtension::Initialize(_Parser);
> -
> - Assembler = nullptr;
> - // FIXME: need better way to detect AsmStreamer (upstream removed
> getKind())
> - if (!Parser.getStreamer().hasRawTextSupport()) {
> - MCELFStreamer *MES = static_cast<MCELFStreamer
> *>(&Parser.getStreamer());
> - Assembler = &MES->getAssembler();
> - }
> }
>
> bool splitIdentifier(OperandVector &Operands);
> @@ -190,6 +190,7 @@ public:
> /// instruction.
> struct HexagonOperand : public MCParsedAsmOperand {
> enum KindTy { Token, Immediate, Register } Kind;
> + MCContext &Context;
>
> SMLoc StartLoc, EndLoc;
>
> @@ -216,10 +217,12 @@ struct HexagonOperand : public MCParsedA
> struct ImmTy Imm;
> };
>
> - HexagonOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
> + HexagonOperand(KindTy K, MCContext &Context)
> + : MCParsedAsmOperand(), Kind(K), Context(Context) {}
>
> public:
> - HexagonOperand(const HexagonOperand &o) : MCParsedAsmOperand() {
> + HexagonOperand(const HexagonOperand &o)
> + : MCParsedAsmOperand(), Context(o.Context) {
> Kind = o.Kind;
> StartLoc = o.StartLoc;
> EndLoc = o.EndLoc;
> @@ -392,9 +395,13 @@ public:
> return;
> }
> int64_t Extended = SignExtend64(Value, 32);
> + HexagonMCExpr *NewExpr = HexagonMCExpr::create(
> + MCConstantExpr::create(Extended, Context), Context);
> if ((Extended < 0) != (Value < 0))
> - Expr->setSignMismatch();
> - Inst.addOperand(MCOperand::createExpr(Expr));
> + NewExpr->setSignMismatch();
> + NewExpr->setMustExtend(Expr->mustExtend());
> + NewExpr->setMustNotExtend(Expr->mustNotExtend());
> + Inst.addOperand(MCOperand::createExpr(NewExpr));
> }
>
> void addn1ConstOperands(MCInst &Inst, unsigned N) const {
> @@ -408,8 +415,9 @@ public:
>
> void print(raw_ostream &OS) const override;
>
> - static std::unique_ptr<HexagonOperand> CreateToken(StringRef Str, SMLoc
> S) {
> - HexagonOperand *Op = new HexagonOperand(Token);
> + static std::unique_ptr<HexagonOperand> CreateToken(MCContext &Context,
> + StringRef Str, SMLoc
> S) {
> + HexagonOperand *Op = new HexagonOperand(Token, Context);
> Op->Tok.Data = Str.data();
> Op->Tok.Length = Str.size();
> Op->StartLoc = S;
> @@ -417,18 +425,18 @@ public:
> return std::unique_ptr<HexagonOperand>(Op);
> }
>
> - static std::unique_ptr<HexagonOperand> CreateReg(unsigned RegNum, SMLoc
> S,
> - SMLoc E) {
> - HexagonOperand *Op = new HexagonOperand(Register);
> + static std::unique_ptr<HexagonOperand>
> + CreateReg(MCContext &Context, unsigned RegNum, SMLoc S, SMLoc E) {
> + HexagonOperand *Op = new HexagonOperand(Register, Context);
> Op->Reg.RegNum = RegNum;
> Op->StartLoc = S;
> Op->EndLoc = E;
> return std::unique_ptr<HexagonOperand>(Op);
> }
>
> - static std::unique_ptr<HexagonOperand> CreateImm(const MCExpr *Val,
> SMLoc S,
> - SMLoc E) {
> - HexagonOperand *Op = new HexagonOperand(Immediate);
> + static std::unique_ptr<HexagonOperand>
> + CreateImm(MCContext &Context, const MCExpr *Val, SMLoc S, SMLoc E) {
> + HexagonOperand *Op = new HexagonOperand(Immediate, Context);
> Op->Imm.Val = Val;
> Op->StartLoc = S;
> Op->EndLoc = E;
> @@ -480,8 +488,8 @@ bool HexagonAsmParser::finishBundle(SMLo
> // 4 or less we have a packet that is too big.
> if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE) {
> Error(IDLoc, "invalid instruction packet: out of slots");
> - return true; // Error
> }
> + return true; // Error
> }
>
> return false; // No error
> @@ -493,13 +501,23 @@ bool HexagonAsmParser::matchBundleOption
> if (!Parser.getTok().is(AsmToken::Colon))
> return false;
> Lex();
> + char const *MemNoShuffMsg =
> + "invalid instruction packet: mem_noshuf specifier not "
> + "supported with this architecture";
> StringRef Option = Parser.getTok().getString();
> + auto IDLoc = Parser.getTok().getLoc();
> if (Option.compare_lower("endloop0") == 0)
> HexagonMCInstrInfo::setInnerLoop(MCB);
> else if (Option.compare_lower("endloop1") == 0)
> HexagonMCInstrInfo::setOuterLoop(MCB);
> + else if (Option.compare_lower("mem_noshuf") == 0)
> + if (getSTI().getFeatureBits()[Hexagon::FeatureMemNoShuf])
> + HexagonMCInstrInfo::setMemReorderDisabled(MCB);
> + else
> + return getParser().Error(IDLoc, MemNoShuffMsg);
> else
> - return true;
> + return getParser().Error(IDLoc, llvm::Twine("'") + Option +
> + "' is not a valid bundle
> option");
> Lex();
> }
> }
> @@ -512,13 +530,13 @@ void HexagonAsmParser::canonicalizeImmed
> NewInst.setOpcode(MCI.getOpcode());
> for (MCOperand &I : MCI)
> if (I.isImm()) {
> - int64_t Value (I.getImm());
> + int64_t Value(I.getImm());
> NewInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(
> MCConstantExpr::create(Value, getContext()), getContext())));
> } else {
> if (I.isExpr() && cast<HexagonMCExpr>(I.getExpr())->signMismatch()
> &&
> WarnSignedMismatch)
> - Warning (MCI.getLoc(), "Signed/Unsigned mismatch");
> + Warning(MCI.getLoc(), "Signed/Unsigned mismatch");
> NewInst.addOperand(I);
> }
> MCI = NewInst;
> @@ -572,6 +590,15 @@ bool HexagonAsmParser::matchOneInstructi
> llvm_unreachable("Implement any new match types added!");
> }
>
> +void HexagonAsmParser::eatToEndOfPacket() {
> + assert(InBrackets);
> + MCAsmLexer &Lexer = getLexer();
> + while (!Lexer.is(AsmToken::RCurly))
> + Lexer.Lex();
> + Lexer.Lex();
> + InBrackets = false;
> +}
> +
> bool HexagonAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned
> &Opcode,
> OperandVector &Operands,
> MCStreamer &Out,
> @@ -586,6 +613,7 @@ bool HexagonAsmParser::MatchAndEmitInstr
> assert(Operands.size() == 1 && "Brackets should be by themselves");
> if (InBrackets) {
> getParser().Error(IDLoc, "Already in a packet");
> + InBrackets = false;
> return true;
> }
> InBrackets = true;
> @@ -604,8 +632,11 @@ bool HexagonAsmParser::MatchAndEmitInstr
> }
> MCInst *SubInst = new (getParser().getContext()) MCInst;
> if (matchOneInstruction(*SubInst, IDLoc, Operands, ErrorInfo,
> - MatchingInlineAsm))
> + MatchingInlineAsm)) {
> + if (InBrackets)
> + eatToEndOfPacket();
> return true;
> + }
> HexagonMCInstrInfo::extendIfNeeded(
> getParser().getContext(), MII, MCB, *SubInst);
> MCB.addOperand(MCOperand::createInst(SubInst));
> @@ -853,10 +884,11 @@ bool HexagonAsmParser::splitIdentifier(O
> do {
> std::pair<StringRef, StringRef> HeadTail = String.split('.');
> if (!HeadTail.first.empty())
> - Operands.push_back(HexagonOperand::CreateToken(HeadTail.first,
> Loc));
> + Operands.push_back(
> + HexagonOperand::CreateToken(getContext(), HeadTail.first, Loc));
> if (!HeadTail.second.empty())
> Operands.push_back(HexagonOperand::CreateToken(
> - String.substr(HeadTail.first.size(), 1), Loc));
> + getContext(), String.substr(HeadTail.first.size(), 1), Loc));
> String = HeadTail.second;
> } while (!String.empty());
> return false;
> @@ -878,38 +910,43 @@ bool HexagonAsmParser::parseOperand(Oper
> case Hexagon::P3:
> if (previousEqual(Operands, 0, "if")) {
> if (WarnMissingParenthesis)
> - Warning (Begin, "Missing parenthesis around predicate
> register");
> + Warning(Begin, "Missing parenthesis around predicate
> register");
> static char const *LParen = "(";
> static char const *RParen = ")";
> - Operands.push_back(HexagonOperand::CreateToken(LParen, Begin));
> - Operands.push_back(HexagonOperand::CreateReg(Register, Begin,
> End));
> + Operands.push_back(
> + HexagonOperand::CreateToken(getContext(), LParen, Begin));
> + Operands.push_back(
> + HexagonOperand::CreateReg(getContext(), Register, Begin,
> End));
> const AsmToken &MaybeDotNew = Lexer.getTok();
> if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&
> MaybeDotNew.getString().equals_lower(".new"))
> splitIdentifier(Operands);
> - Operands.push_back(HexagonOperand::CreateToken(RParen, Begin));
> + Operands.push_back(
> + HexagonOperand::CreateToken(getContext(), RParen, Begin));
> return false;
> }
> if (previousEqual(Operands, 0, "!") &&
> previousEqual(Operands, 1, "if")) {
> if (WarnMissingParenthesis)
> - Warning (Begin, "Missing parenthesis around predicate
> register");
> + Warning(Begin, "Missing parenthesis around predicate
> register");
> static char const *LParen = "(";
> static char const *RParen = ")";
> - Operands.insert(Operands.end () - 1,
> - HexagonOperand::CreateToken(LParen, Begin));
> - Operands.push_back(HexagonOperand::CreateReg(Register, Begin,
> End));
> + Operands.insert(Operands.end() - 1, HexagonOperand::CreateToken(
> + getContext(), LParen,
> Begin));
> + Operands.push_back(
> + HexagonOperand::CreateReg(getContext(), Register, Begin,
> End));
> const AsmToken &MaybeDotNew = Lexer.getTok();
> if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&
> MaybeDotNew.getString().equals_lower(".new"))
> splitIdentifier(Operands);
> - Operands.push_back(HexagonOperand::CreateToken(RParen, Begin));
> + Operands.push_back(
> + HexagonOperand::CreateToken(getContext(), RParen, Begin));
> return false;
> }
> break;
> }
> - Operands.push_back(HexagonOperand::CreateReg(
> - Register, Begin, End));
> + Operands.push_back(
> + HexagonOperand::CreateReg(getContext(), Register, Begin, End));
> return false;
> }
> return splitIdentifier(Operands);
> @@ -931,10 +968,9 @@ bool HexagonAsmParser::isLabel(AsmToken
> return true;
> if (!matchRegister(String.lower()))
> return true;
> - (void)Second;
> assert(Second.is(AsmToken::Colon));
> - StringRef Raw (String.data(), Third.getString().data() - String.data() +
> - Third.getString().size());
> + StringRef Raw(String.data(), Third.getString().data() - String.data() +
> + Third.getString().size());
> std::string Collapsed = Raw;
> Collapsed.erase(llvm::remove_if(Collapsed, isspace), Collapsed.end());
> StringRef Whole = Collapsed;
> @@ -944,7 +980,8 @@ bool HexagonAsmParser::isLabel(AsmToken
> return false;
> }
>
> -bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious, SMLoc
> &Loc) {
> +bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious,
> + SMLoc &Loc) {
> if (!Contigious && ErrorNoncontigiousRegister) {
> Error(Loc, "Register name is not contigious");
> return true;
> @@ -954,7 +991,8 @@ bool HexagonAsmParser::handleNoncontigio
> return false;
> }
>
> -bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
> SMLoc &EndLoc) {
> +bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
> + SMLoc &EndLoc) {
> MCAsmLexer &Lexer = getLexer();
> StartLoc = getLexer().getLoc();
> SmallVector<AsmToken, 5> Lookahead;
> @@ -963,19 +1001,19 @@ bool HexagonAsmParser::ParseRegister(uns
> bool NeededWorkaround = false;
> while (Again) {
> AsmToken const &Token = Lexer.getTok();
> - RawString = StringRef(RawString.data(),
> - Token.getString().data() - RawString.data () +
> - Token.getString().size());
> + RawString = StringRef(RawString.data(), Token.getString().data() -
> + RawString.data() +
> + Token.getString().size());
> Lookahead.push_back(Token);
> Lexer.Lex();
> bool Contigious = Lexer.getTok().getString().data() ==
> Lookahead.back().getString().data() +
> - Lookahead.back().getString().size();
> + Lookahead.back().getString().size();
> bool Type = Lexer.is(AsmToken::Identifier) || Lexer.is(AsmToken::Dot)
> ||
> Lexer.is(AsmToken::Integer) || Lexer.is(AsmToken::Real) ||
> Lexer.is(AsmToken::Colon);
> - bool Workaround = Lexer.is(AsmToken::Colon) ||
> - Lookahead.back().is(AsmToken::Colon);
> + bool Workaround =
> + Lexer.is(AsmToken::Colon) || Lookahead.back().is(AsmToken::Colon);
> Again = (Contigious && Type) || (Workaround && Type);
> NeededWorkaround = NeededWorkaround || (Again && !(Contigious &&
> Type));
> }
> @@ -1005,10 +1043,10 @@ bool HexagonAsmParser::ParseRegister(uns
> std::pair<StringRef, StringRef> ColonSplit =
> StringRef(FullString).split(':');
> unsigned ColonReg = matchRegister(ColonSplit.first.lower());
> if (ColonReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
> - Lexer.UnLex(Lookahead.back());
> - Lookahead.pop_back();
> - Lexer.UnLex(Lookahead.back());
> - Lookahead.pop_back();
> + do {
> + Lexer.UnLex(Lookahead.back());
> + Lookahead.pop_back();
> + } while (!Lookahead.empty () && !Lexer.is(AsmToken::Colon));
> RegNo = ColonReg;
> EndLoc = Lexer.getLoc();
> if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
> @@ -1036,19 +1074,18 @@ bool HexagonAsmParser::implicitExpressio
> return false;
> }
>
> -bool HexagonAsmParser::parseExpression(MCExpr const *& Expr) {
> +bool HexagonAsmParser::parseExpression(MCExpr const *&Expr) {
> SmallVector<AsmToken, 4> Tokens;
> MCAsmLexer &Lexer = getLexer();
> bool Done = false;
> - static char const * Comma = ",";
> + static char const *Comma = ",";
> do {
> - Tokens.emplace_back (Lexer.getTok());
> + Tokens.emplace_back(Lexer.getTok());
> Lex();
> - switch (Tokens.back().getKind())
> - {
> + switch (Tokens.back().getKind()) {
> case AsmToken::TokenKind::Hash:
> - if (Tokens.size () > 1)
> - if ((Tokens.end () - 2)->getKind() == AsmToken::TokenKind::Plus) {
> + if (Tokens.size() > 1)
> + if ((Tokens.end() - 2)->getKind() == AsmToken::TokenKind::Plus) {
> Tokens.insert(Tokens.end() - 2,
> AsmToken(AsmToken::TokenKind::Comma, Comma));
> Done = true;
> @@ -1067,7 +1104,8 @@ bool HexagonAsmParser::parseExpression(M
> Lexer.UnLex(Tokens.back());
> Tokens.pop_back();
> }
> - return getParser().parseExpression(Expr);
> + SMLoc Loc = Lexer.getLoc();
> + return getParser().parseExpression(Expr, Loc);
> }
>
> bool HexagonAsmParser::parseExpressionOrOperand(OperandVector &Operands) {
> @@ -1078,7 +1116,8 @@ bool HexagonAsmParser::parseExpressionOr
> bool Error = parseExpression(Expr);
> Expr = HexagonMCExpr::create(Expr, getContext());
> if (!Error)
> - Operands.push_back(HexagonOperand::CreateImm(Expr, Loc, Loc));
> + Operands.push_back(
> + HexagonOperand::CreateImm(getContext(), Expr, Loc, Loc));
> return Error;
> }
> return parseOperand(Operands);
> @@ -1091,6 +1130,7 @@ bool HexagonAsmParser::parseInstruction(
> while (true) {
> AsmToken const &Token = Parser.getTok();
> switch (Token.getKind()) {
> + case AsmToken::Eof:
> case AsmToken::EndOfStatement: {
> Lex();
> return false;
> @@ -1098,15 +1138,15 @@ bool HexagonAsmParser::parseInstruction(
> case AsmToken::LCurly: {
> if (!Operands.empty())
> return true;
> - Operands.push_back(
> - HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));
> + Operands.push_back(HexagonOperand::CreateToken(
> + getContext(), Token.getString(), Token.getLoc()));
> Lex();
> return false;
> }
> case AsmToken::RCurly: {
> if (Operands.empty()) {
> - Operands.push_back(
> - HexagonOperand::CreateToken(Token.getString(),
> Token.getLoc()));
> + Operands.push_back(HexagonOperand::CreateToken(
> + getContext(), Token.getString(), Token.getLoc()));
> Lex();
> }
> return false;
> @@ -1122,9 +1162,9 @@ bool HexagonAsmParser::parseInstruction(
> case AsmToken::LessEqual:
> case AsmToken::LessLess: {
> Operands.push_back(HexagonOperand::CreateToken(
> - Token.getString().substr(0, 1), Token.getLoc()));
> + getContext(), Token.getString().substr(0, 1), Token.getLoc()));
> Operands.push_back(HexagonOperand::CreateToken(
> - Token.getString().substr(1, 1), Token.getLoc()));
> + getContext(), Token.getString().substr(1, 1), Token.getLoc()));
> Lex();
> continue;
> }
> @@ -1133,8 +1173,8 @@ bool HexagonAsmParser::parseInstruction(
> bool ImplicitExpression = implicitExpressionLocation(Operands);
> SMLoc ExprLoc = Lexer.getLoc();
> if (!ImplicitExpression)
> - Operands.push_back(
> - HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));
> + Operands.push_back(HexagonOperand::CreateToken(
> + getContext(), Token.getString(), Token.getLoc()));
> Lex();
> bool MustExtend = false;
> bool HiOnly = false;
> @@ -1171,16 +1211,15 @@ bool HexagonAsmParser::parseInstruction(
> if (Expr->evaluateAsAbsolute(Value)) {
> if (HiOnly)
> Expr = MCBinaryExpr::createLShr(
> - Expr, MCConstantExpr::create(16, Context), Context);
> + Expr, MCConstantExpr::create(16, Context), Context);
> if (HiOnly || LoOnly)
> - Expr = MCBinaryExpr::createAnd(Expr,
> - MCConstantExpr::create(0xffff, Context),
> - Context);
> + Expr = MCBinaryExpr::createAnd(
> + Expr, MCConstantExpr::create(0xffff, Context), Context);
> } else {
> MCValue Value;
> if (Expr->evaluateAsRelocatable(Value, nullptr, nullptr)) {
> if (!Value.isAbsolute()) {
> - switch(Value.getAccessVariant()) {
> + switch (Value.getAccessVariant()) {
> case MCSymbolRefExpr::VariantKind::VK_TPREL:
> case MCSymbolRefExpr::VariantKind::VK_DTPREL:
> // Don't lazy extend these expression variants
> @@ -1196,7 +1235,7 @@ bool HexagonAsmParser::parseInstruction(
> HexagonMCInstrInfo::setMustNotExtend(*Expr, MustNotExtend);
> HexagonMCInstrInfo::setMustExtend(*Expr, MustExtend);
> std::unique_ptr<HexagonOperand> Operand =
> - HexagonOperand::CreateImm(Expr, ExprLoc, ExprLoc);
> + HexagonOperand::CreateImm(getContext(), Expr, ExprLoc, ExprLoc);
> Operands.push_back(std::move(Operand));
> continue;
> }
> @@ -1209,15 +1248,14 @@ bool HexagonAsmParser::parseInstruction(
> }
>
> bool HexagonAsmParser::ParseInstruction(ParseInstructionInfo &Info,
> - StringRef Name,
> - AsmToken ID,
> + StringRef Name, AsmToken ID,
> OperandVector &Operands) {
> getLexer().UnLex(ID);
> return parseInstruction(Operands);
> }
>
> -static MCInst makeCombineInst(int opCode, MCOperand &Rdd,
> - MCOperand &MO1, MCOperand &MO2) {
> +static MCInst makeCombineInst(int opCode, MCOperand &Rdd, MCOperand &MO1,
> + MCOperand &MO2) {
> MCInst TmpInst;
> TmpInst.setOpcode(opCode);
> TmpInst.addOperand(Rdd);
> @@ -1286,6 +1324,13 @@ int HexagonAsmParser::processInstruction
> bool is32bit = false; // used to distinguish between CONST32 and CONST64
> switch (Inst.getOpcode()) {
> default:
> + if (HexagonMCInstrInfo::getDesc(MII, Inst).isPseudo()) {
> + SMDiagnostic Diag = getSourceManager().GetMessage(
> +
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