<div dir="ltr">For the record you really should have broken this up into separate commits. <div><br></div><div> 69 files changed, 13364 insertions(+), 5905 deletions(-)</div><div><br></div><div>-eric</div><div><br><div class="gmail_quote"><div dir="ltr">On Mon, Dec 11, 2017 at 10:58 AM Krzysztof Parzyszek via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: kparzysz<br>
Date: Mon Dec 11 10:57:54 2017<br>
New Revision: 320404<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=320404&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=320404&view=rev</a><br>
Log:<br>
[Hexagon] Add support for Hexagon V65<br>
<br>
Added:<br>
llvm/trunk/lib/Target/Hexagon/HexagonDepDecoders.h<br>
llvm/trunk/lib/Target/Hexagon/HexagonGatherPacketize.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV65.td<br>
llvm/trunk/lib/Target/Hexagon/<a href="http://HexagonMapAsm2IntrinV65.gen.td" rel="noreferrer" target="_blank">HexagonMapAsm2IntrinV65.gen.td</a><br>
llvm/trunk/lib/Target/Hexagon/HexagonPatternsV65.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonScheduleV65.td<br>
llvm/trunk/test/CodeGen/Hexagon/intrinsics/v65-gather-double.ll<br>
llvm/trunk/test/CodeGen/Hexagon/intrinsics/v65-gather.ll<br>
llvm/trunk/test/CodeGen/Hexagon/intrinsics/v65-scatter-double.ll<br>
llvm/trunk/test/CodeGen/Hexagon/intrinsics/v65-scatter-gather.ll<br>
llvm/trunk/test/CodeGen/Hexagon/intrinsics/v65-scatter.ll<br>
llvm/trunk/test/CodeGen/Hexagon/intrinsics/v65.ll<br>
llvm/trunk/test/MC/Hexagon/hvx-double-implies-hvx.s<br>
llvm/trunk/test/MC/Hexagon/v65_all.s<br>
llvm/trunk/test/MC/Hexagon/vpred_defs.s<br>
llvm/trunk/test/MC/Hexagon/vscatter-slot.s<br>
llvm/trunk/test/MC/Hexagon/vtmp_def.s<br>
Modified:<br>
llvm/trunk/include/llvm/BinaryFormat/ELF.h<br>
llvm/trunk/include/llvm/IR/IntrinsicsHexagon.td<br>
llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp<br>
llvm/trunk/lib/Target/Hexagon/CMakeLists.txt<br>
llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp<br>
llvm/trunk/lib/Target/Hexagon/Hexagon.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonDepArch.h<br>
llvm/trunk/lib/Target/Hexagon/HexagonDepArch.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonDepIICHVX.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonDepIICScalar.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonDepITypes.h<br>
llvm/trunk/lib/Target/Hexagon/HexagonDepITypes.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonDepInstrFormats.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonDepInstrInfo.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonDepMappings.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonDepOperands.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonDepTimingClasses.h<br>
llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonIICHVX.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.h<br>
llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h<br>
llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h<br>
llvm/trunk/lib/Target/Hexagon/HexagonIntrinsics.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonSchedule.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h<br>
llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.h<br>
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp<br>
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h<br>
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp<br>
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h<br>
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp<br>
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp<br>
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h<br>
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp<br>
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h<br>
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp<br>
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h<br>
llvm/trunk/test/CodeGen/Hexagon/livephysregs-lane-masks.mir<br>
llvm/trunk/test/MC/Hexagon/PacketRules/endloop_branches.s<br>
llvm/trunk/test/MC/Hexagon/new-value-check.s<br>
llvm/trunk/test/MC/Hexagon/v60-misc.s<br>
<br>
Modified: llvm/trunk/include/llvm/BinaryFormat/ELF.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/BinaryFormat/ELF.h?rev=320404&r1=320403&r2=320404&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/BinaryFormat/ELF.h?rev=320404&r1=320403&r2=320404&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/BinaryFormat/ELF.h (original)<br>
+++ llvm/trunk/include/llvm/BinaryFormat/ELF.h Mon Dec 11 10:57:54 2017<br>
@@ -584,6 +584,7 @@ enum {<br>
EF_HEXAGON_MACH_V55 = 0x00000005, // Hexagon V55<br>
EF_HEXAGON_MACH_V60 = 0x00000060, // Hexagon V60<br>
EF_HEXAGON_MACH_V62 = 0x00000062, // Hexagon V62<br>
+ EF_HEXAGON_MACH_V65 = 0x00000065, // Hexagon V65<br>
<br>
// Highest ISA version flags<br>
EF_HEXAGON_ISA_MACH = 0x00000000, // Same as specified in bits[11:0]<br>
@@ -595,6 +596,7 @@ enum {<br>
EF_HEXAGON_ISA_V55 = 0x00000050, // Hexagon V55 ISA<br>
EF_HEXAGON_ISA_V60 = 0x00000060, // Hexagon V60 ISA<br>
EF_HEXAGON_ISA_V62 = 0x00000062, // Hexagon V62 ISA<br>
+ EF_HEXAGON_ISA_V65 = 0x00000065, // Hexagon V65 ISA<br>
};<br>
<br>
// Hexagon-specific section indexes for common small data<br>
<br>
Modified: llvm/trunk/include/llvm/IR/IntrinsicsHexagon.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsHexagon.td?rev=320404&r1=320403&r2=320404&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsHexagon.td?rev=320404&r1=320403&r2=320404&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/IR/IntrinsicsHexagon.td (original)<br>
+++ llvm/trunk/include/llvm/IR/IntrinsicsHexagon.td Mon Dec 11 10:57:54 2017<br>
@@ -5044,7 +5044,6 @@ def int_hexagon_V6_vassignp_128B :<br>
Hexagon_v2048v2048_Intrinsic_T<"HEXAGON_V6_vassignp_128B">;<br>
<br>
<br>
-<br>
//<br>
// Hexagon_iii_Intrinsic<string GCCIntSuffix><br>
// tag : S6_rol_i_r<br>
@@ -5583,54 +5582,6 @@ class Hexagon_v1024i_Intrinsic<string GC<br>
[IntrNoMem]>;<br>
<br>
//<br>
-// Hexagon_v512v512LLii_Intrinsic<string GCCIntSuffix><br>
-// tag : V6_vlutb<br>
-class Hexagon_v512v512LLii_Intrinsic<string GCCIntSuffix><br>
- : Hexagon_Intrinsic<GCCIntSuffix,<br>
- [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i64_ty,llvm_i32_ty],<br>
- [IntrNoMem]>;<br>
-<br>
-//<br>
-// Hexagon_v1024v1024LLii_Intrinsic<string GCCIntSuffix><br>
-// tag : V6_vlutb_128B<br>
-class Hexagon_v1024v1024LLii_Intrinsic<string GCCIntSuffix><br>
- : Hexagon_Intrinsic<GCCIntSuffix,<br>
- [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i64_ty,llvm_i32_ty],<br>
- [IntrNoMem]>;<br>
-<br>
-//<br>
-// Hexagon_v512v512v512LLii_Intrinsic<string GCCIntSuffix><br>
-// tag : V6_vlutb_acc<br>
-class Hexagon_v512v512v512LLii_Intrinsic<string GCCIntSuffix><br>
- : Hexagon_Intrinsic<GCCIntSuffix,<br>
- [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i64_ty,llvm_i32_ty],<br>
- [IntrNoMem]>;<br>
-<br>
-//<br>
-// Hexagon_v1024v1024v1024LLii_Intrinsic<string GCCIntSuffix><br>
-// tag : V6_vlutb_acc_128B<br>
-class Hexagon_v1024v1024v1024LLii_Intrinsic<string GCCIntSuffix><br>
- : Hexagon_Intrinsic<GCCIntSuffix,<br>
- [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i64_ty,llvm_i32_ty],<br>
- [IntrNoMem]>;<br>
-<br>
-//<br>
-// Hexagon_v2048v2048LLii_Intrinsic<string GCCIntSuffix><br>
-// tag : V6_vlutb_dv_128B<br>
-class Hexagon_v2048v2048LLii_Intrinsic<string GCCIntSuffix><br>
- : Hexagon_Intrinsic<GCCIntSuffix,<br>
- [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i64_ty,llvm_i32_ty],<br>
- [IntrNoMem]>;<br>
-<br>
-//<br>
-// Hexagon_v2048v2048v2048LLii_Intrinsic<string GCCIntSuffix><br>
-// tag : V6_vlutb_dv_acc_128B<br>
-class Hexagon_v2048v2048v2048LLii_Intrinsic<string GCCIntSuffix><br>
- : Hexagon_Intrinsic<GCCIntSuffix,<br>
- [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i64_ty,llvm_i32_ty],<br>
- [IntrNoMem]>;<br>
-<br>
-//<br>
// Hexagon_v512v512v512v512i_Intrinsic<string GCCIntSuffix><br>
// tag : V6_vlutvvb_oracc<br>
class Hexagon_v512v512v512v512i_Intrinsic<string GCCIntSuffix><br>
@@ -9167,54 +9118,6 @@ def int_hexagon_V6_vcombine_128B :<br>
Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vcombine_128B">;<br>
<br>
//<br>
-// BUILTIN_INFO(HEXAGON.V6_vlutb,VI_ftype_VIDISI,3)<br>
-// tag : V6_vlutb<br>
-def int_hexagon_V6_vlutb :<br>
-Hexagon_v512v512LLii_Intrinsic<"HEXAGON_V6_vlutb">;<br>
-<br>
-//<br>
-// BUILTIN_INFO(HEXAGON.V6_vlutb_128B,VI_ftype_VIDISI,3)<br>
-// tag : V6_vlutb_128B<br>
-def int_hexagon_V6_vlutb_128B :<br>
-Hexagon_v1024v1024LLii_Intrinsic<"HEXAGON_V6_vlutb_128B">;<br>
-<br>
-//<br>
-// BUILTIN_INFO(HEXAGON.V6_vlutb_acc,VI_ftype_VIVIDISI,4)<br>
-// tag : V6_vlutb_acc<br>
-def int_hexagon_V6_vlutb_acc :<br>
-Hexagon_v512v512v512LLii_Intrinsic<"HEXAGON_V6_vlutb_acc">;<br>
-<br>
-//<br>
-// BUILTIN_INFO(HEXAGON.V6_vlutb_acc_128B,VI_ftype_VIVIDISI,4)<br>
-// tag : V6_vlutb_acc_128B<br>
-def int_hexagon_V6_vlutb_acc_128B :<br>
-Hexagon_v1024v1024v1024LLii_Intrinsic<"HEXAGON_V6_vlutb_acc_128B">;<br>
-<br>
-//<br>
-// BUILTIN_INFO(HEXAGON.V6_vlutb_dv,VD_ftype_VDDISI,3)<br>
-// tag : V6_vlutb_dv<br>
-def int_hexagon_V6_vlutb_dv :<br>
-Hexagon_v1024v1024LLii_Intrinsic<"HEXAGON_V6_vlutb_dv">;<br>
-<br>
-//<br>
-// BUILTIN_INFO(HEXAGON.V6_vlutb_dv_128B,VD_ftype_VDDISI,3)<br>
-// tag : V6_vlutb_dv_128B<br>
-def int_hexagon_V6_vlutb_dv_128B :<br>
-Hexagon_v2048v2048LLii_Intrinsic<"HEXAGON_V6_vlutb_dv_128B">;<br>
-<br>
-//<br>
-// BUILTIN_INFO(HEXAGON.V6_vlutb_dv_acc,VD_ftype_VDVDDISI,4)<br>
-// tag : V6_vlutb_dv_acc<br>
-def int_hexagon_V6_vlutb_dv_acc :<br>
-Hexagon_v1024v1024v1024LLii_Intrinsic<"HEXAGON_V6_vlutb_dv_acc">;<br>
-<br>
-//<br>
-// BUILTIN_INFO(HEXAGON.V6_vlutb_dv_acc_128B,VD_ftype_VDVDDISI,4)<br>
-// tag : V6_vlutb_dv_acc_128B<br>
-def int_hexagon_V6_vlutb_dv_acc_128B :<br>
-Hexagon_v2048v2048v2048LLii_Intrinsic<"HEXAGON_V6_vlutb_dv_acc_128B">;<br>
-<br>
-//<br>
// BUILTIN_INFO(HEXAGON.V6_vdelta,VI_ftype_VIVI,2)<br>
// tag : V6_vdelta<br>
def int_hexagon_V6_vdelta :<br>
@@ -9349,6 +9252,30 @@ Hexagon_v2048v2048v1024v1024i_Intrinsic<<br>
//<br>
// Masked vector stores<br>
//<br>
+def int_hexagon_V6_vS32b_qpred_ai :<br>
+Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai">;<br>
+<br>
+def int_hexagon_V6_vS32b_nqpred_ai :<br>
+Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai">;<br>
+<br>
+def int_hexagon_V6_vS32b_nt_qpred_ai :<br>
+Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai">;<br>
+<br>
+def int_hexagon_V6_vS32b_nt_nqpred_ai :<br>
+Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai">;<br>
+<br>
+def int_hexagon_V6_vS32b_qpred_ai_128B :<br>
+Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai_128B">;<br>
+<br>
+def int_hexagon_V6_vS32b_nqpred_ai_128B :<br>
+Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai_128B">;<br>
+<br>
+def int_hexagon_V6_vS32b_nt_qpred_ai_128B :<br>
+Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai_128B">;<br>
+<br>
+def int_hexagon_V6_vS32b_nt_nqpred_ai_128B :<br>
+Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai_128B">;<br>
+<br>
def int_hexagon_V6_vmaskedstoreq :<br>
Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstoreq">;<br>
<br>
@@ -9642,6 +9569,20 @@ class Hexagon_V62_v2048v2048v1024v1024i_<br>
[llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],<br>
[IntrNoMem]>;<br>
<br>
+// Hexagon_v512v64iv512v512v64i_Intrinsic<string GCCIntSuffix><br>
+// tag: V6_vaddcarry<br>
+class Hexagon_v512v64iv512v512v64i_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_v16i32_ty, llvm_v512i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v512i1_ty],<br>
+ [IntrNoMem]>;<br>
+<br>
+// Hexagon_v1024v128iv1024v1024v128i_Intrinsic<string GCCIntSuffix><br>
+// tag: V6_vaddcarry_128B<br>
+class Hexagon_v1024v128iv1024v1024v128i_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_v32i32_ty, llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v1024i1_ty],<br>
+ [IntrNoMem]>;<br>
+<br>
<br>
//<br>
// BUILTIN_INFO(HEXAGON.M6_vabsdiffb,DI_ftype_DIDI,2)<br>
@@ -10213,3 +10154,821 @@ Hexagon_V62_v1024v512v512i_Intrinsic<"HE<br>
def int_hexagon_V6_vlutvwh_nm_128B :<br>
Hexagon_V62_v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvwh_nm_128B">;<br>
<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vaddcarry,VI_ftype_VIVIQV,3)<br>
+// tag: V6_vaddcarry<br>
+def int_hexagon_V6_vaddcarry :<br>
+Hexagon_v512v64iv512v512v64i_Intrinsic<"HEXAGON_v6_vaddcarry">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vaddcarry_128B,VI_ftype_VIVIQV,3)<br>
+// tag: V6_vaddcarry_128B<br>
+def int_hexagon_V6_vaddcarry_128B :<br>
+Hexagon_v1024v128iv1024v1024v128i_Intrinsic<"HEXAGON_v6_vaddcarry_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vsubcarry,VI_ftype_VIVIQV,3)<br>
+// tag: V6_vsubcarry<br>
+def int_hexagon_V6_vsubcarry :<br>
+Hexagon_v512v64iv512v512v64i_Intrinsic<"HEXAGON_v6_vsubcarry">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vsubcarry_128B,VI_ftype_VIVIQV,3)<br>
+// tag: V6_vsubcarry_128B<br>
+def int_hexagon_V6_vsubcarry_128B :<br>
+Hexagon_v1024v128iv1024v1024v128i_Intrinsic<"HEXAGON_v6_vsubcarry_128B">;<br>
+<br>
+<br>
+///<br>
+/// HexagonV65 intrinsics<br>
+///<br>
+<br>
+//<br>
+// Hexagon_V65_iLLiLLi_Intrinsic<string GCCIntSuffix><br>
+// tag : A6_vcmpbeq_notany<br>
+class Hexagon_V65_iLLiLLi_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty],<br>
+ [IntrNoMem]>;<br>
+<br>
+//<br>
+// Hexagon_V65_v1024v512LLi_Intrinsic<string GCCIntSuffix><br>
+// tag : V6_vrmpyub_rtt<br>
+class Hexagon_V65_v1024v512LLi_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i64_ty],<br>
+ [IntrNoMem]>;<br>
+<br>
+//<br>
+// Hexagon_V65_v2048v1024LLi_Intrinsic<string GCCIntSuffix><br>
+// tag : V6_vrmpyub_rtt_128B<br>
+class Hexagon_V65_v2048v1024LLi_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i64_ty],<br>
+ [IntrNoMem]>;<br>
+<br>
+//<br>
+// Hexagon_V65_v1024v1024v512LLi_Intrinsic<string GCCIntSuffix><br>
+// tag : V6_vrmpyub_rtt_acc<br>
+class Hexagon_V65_v1024v1024v512LLi_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i64_ty],<br>
+ [IntrNoMem]>;<br>
+<br>
+//<br>
+// Hexagon_V65_v2048v2048v1024LLi_Intrinsic<string GCCIntSuffix><br>
+// tag : V6_vrmpyub_rtt_acc_128B<br>
+class Hexagon_V65_v2048v2048v1024LLi_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i64_ty],<br>
+ [IntrNoMem]>;<br>
+<br>
+//<br>
+// Hexagon_V65_v512v512v512i_Intrinsic<string GCCIntSuffix><br>
+// tag : V6_vasruwuhsat<br>
+class Hexagon_V65_v512v512v512i_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],<br>
+ [IntrNoMem]>;<br>
+<br>
+//<br>
+// Hexagon_V65_v1024v1024v1024i_Intrinsic<string GCCIntSuffix><br>
+// tag : V6_vasruwuhsat_128B<br>
+class Hexagon_V65_v1024v1024v1024i_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],<br>
+ [IntrNoMem]>;<br>
+<br>
+//<br>
+// Hexagon_V65_v512v512v512_Intrinsic<string GCCIntSuffix><br>
+// tag : V6_vavguw<br>
+class Hexagon_V65_v512v512v512_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],<br>
+ [IntrNoMem]>;<br>
+<br>
+//<br>
+// Hexagon_V65_v1024v1024v1024_Intrinsic<string GCCIntSuffix><br>
+// tag : V6_vavguw_128B<br>
+class Hexagon_V65_v1024v1024v1024_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],<br>
+ [IntrNoMem]>;<br>
+<br>
+//<br>
+// Hexagon_V65_v512v512_Intrinsic<string GCCIntSuffix><br>
+// tag : V6_vabsb<br>
+class Hexagon_V65_v512v512_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_v16i32_ty], [llvm_v16i32_ty],<br>
+ [IntrNoMem]>;<br>
+<br>
+//<br>
+// Hexagon_V65_v1024v1024_Intrinsic<string GCCIntSuffix><br>
+// tag : V6_vabsb_128B<br>
+class Hexagon_V65_v1024v1024_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_v32i32_ty], [llvm_v32i32_ty],<br>
+ [IntrNoMem]>;<br>
+<br>
+//<br>
+// Hexagon_V65_v1024v1024i_Intrinsic<string GCCIntSuffix><br>
+// tag : V6_vmpabuu<br>
+class Hexagon_V65_v1024v1024i_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty],<br>
+ [IntrNoMem]>;<br>
+<br>
+//<br>
+// Hexagon_V65_v2048v2048i_Intrinsic<string GCCIntSuffix><br>
+// tag : V6_vmpabuu_128B<br>
+class Hexagon_V65_v2048v2048i_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty],<br>
+ [IntrNoMem]>;<br>
+<br>
+//<br>
+// Hexagon_V65_v2048v2048v2048i_Intrinsic<string GCCIntSuffix><br>
+// tag : V6_vmpabuu_acc_128B<br>
+class Hexagon_V65_v2048v2048v2048i_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty],<br>
+ [IntrNoMem]>;<br>
+<br>
+//<br>
+// Hexagon_V65_v1024v1024v512i_Intrinsic<string GCCIntSuffix><br>
+// tag : V6_vmpyh_acc<br>
+class Hexagon_V65_v1024v1024v512i_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i32_ty],<br>
+ [IntrNoMem]>;<br>
+<br>
+//<br>
+// Hexagon_V65_v2048v2048v1024i_Intrinsic<string GCCIntSuffix><br>
+// tag : V6_vmpyh_acc_128B<br>
+class Hexagon_V65_v2048v2048v1024i_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i32_ty],<br>
+ [IntrNoMem]>;<br>
+<br>
+//<br>
+// Hexagon_V65_v512v512v512LLi_Intrinsic<string GCCIntSuffix><br>
+// tag : V6_vmpahhsat<br>
+class Hexagon_V65_v512v512v512LLi_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i64_ty],<br>
+ [IntrNoMem]>;<br>
+<br>
+//<br>
+// Hexagon_V65_v1024v1024v1024LLi_Intrinsic<string GCCIntSuffix><br>
+// tag : V6_vmpahhsat_128B<br>
+class Hexagon_V65_v1024v1024v1024LLi_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i64_ty],<br>
+ [IntrNoMem]>;<br>
+<br>
+//<br>
+// Hexagon_V65_v512v512LLi_Intrinsic<string GCCIntSuffix><br>
+// tag : V6_vlut4<br>
+class Hexagon_V65_v512v512LLi_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i64_ty],<br>
+ [IntrNoMem]>;<br>
+<br>
+//<br>
+// Hexagon_V65_v1024v1024LLi_Intrinsic<string GCCIntSuffix><br>
+// tag : V6_vlut4_128B<br>
+class Hexagon_V65_v1024v1024LLi_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i64_ty],<br>
+ [IntrNoMem]>;<br>
+<br>
+//<br>
+// Hexagon_V65_v512v512i_Intrinsic<string GCCIntSuffix><br>
+// tag : V6_vmpyuhe<br>
+class Hexagon_V65_v512v512i_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i32_ty],<br>
+ [IntrNoMem]>;<br>
+<br>
+//<br>
+// Hexagon_V65_v512v64i_Intrinsic<string GCCIntSuffix><br>
+// tag : V6_vprefixqb<br>
+class Hexagon_V65_v512v64i_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_v16i32_ty], [llvm_v512i1_ty],<br>
+ [IntrNoMem]>;<br>
+<br>
+//<br>
+// Hexagon_V65_v1024v128i_Intrinsic<string GCCIntSuffix><br>
+// tag : V6_vprefixqb_128B<br>
+class Hexagon_V65_v1024v128i_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_v32i32_ty], [llvm_v1024i1_ty],<br>
+ [IntrNoMem]>;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.A6_vcmpbeq_notany,QI_ftype_DIDI,2)<br>
+// tag : A6_vcmpbeq_notany<br>
+def int_hexagon_A6_vcmpbeq_notany :<br>
+Hexagon_V65_iLLiLLi_Intrinsic<"HEXAGON_A6_vcmpbeq_notany">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.A6_vcmpbeq_notany_128B,QI_ftype_DIDI,2)<br>
+// tag : A6_vcmpbeq_notany_128B<br>
+def int_hexagon_A6_vcmpbeq_notany_128B :<br>
+Hexagon_V65_iLLiLLi_Intrinsic<"HEXAGON_A6_vcmpbeq_notany_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt,VD_ftype_VIDI,2)<br>
+// tag : V6_vrmpyub_rtt<br>
+def int_hexagon_V6_vrmpyub_rtt :<br>
+Hexagon_V65_v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt_128B,VD_ftype_VIDI,2)<br>
+// tag : V6_vrmpyub_rtt_128B<br>
+def int_hexagon_V6_vrmpyub_rtt_128B :<br>
+Hexagon_V65_v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt_acc,VD_ftype_VDVIDI,3)<br>
+// tag : V6_vrmpyub_rtt_acc<br>
+def int_hexagon_V6_vrmpyub_rtt_acc :<br>
+Hexagon_V65_v1024v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt_acc_128B,VD_ftype_VDVIDI,3)<br>
+// tag : V6_vrmpyub_rtt_acc_128B<br>
+def int_hexagon_V6_vrmpyub_rtt_acc_128B :<br>
+Hexagon_V65_v2048v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt,VD_ftype_VIDI,2)<br>
+// tag : V6_vrmpybub_rtt<br>
+def int_hexagon_V6_vrmpybub_rtt :<br>
+Hexagon_V65_v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt_128B,VD_ftype_VIDI,2)<br>
+// tag : V6_vrmpybub_rtt_128B<br>
+def int_hexagon_V6_vrmpybub_rtt_128B :<br>
+Hexagon_V65_v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt_acc,VD_ftype_VDVIDI,3)<br>
+// tag : V6_vrmpybub_rtt_acc<br>
+def int_hexagon_V6_vrmpybub_rtt_acc :<br>
+Hexagon_V65_v1024v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt_acc_128B,VD_ftype_VDVIDI,3)<br>
+// tag : V6_vrmpybub_rtt_acc_128B<br>
+def int_hexagon_V6_vrmpybub_rtt_acc_128B :<br>
+Hexagon_V65_v2048v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vasruwuhsat,VI_ftype_VIVISI,3)<br>
+// tag : V6_vasruwuhsat<br>
+def int_hexagon_V6_vasruwuhsat :<br>
+Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasruwuhsat">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vasruwuhsat_128B,VI_ftype_VIVISI,3)<br>
+// tag : V6_vasruwuhsat_128B<br>
+def int_hexagon_V6_vasruwuhsat_128B :<br>
+Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasruwuhsat_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vasruhubsat,VI_ftype_VIVISI,3)<br>
+// tag : V6_vasruhubsat<br>
+def int_hexagon_V6_vasruhubsat :<br>
+Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasruhubsat">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vasruhubsat_128B,VI_ftype_VIVISI,3)<br>
+// tag : V6_vasruhubsat_128B<br>
+def int_hexagon_V6_vasruhubsat_128B :<br>
+Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasruhubsat_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vasruhubrndsat,VI_ftype_VIVISI,3)<br>
+// tag : V6_vasruhubrndsat<br>
+def int_hexagon_V6_vasruhubrndsat :<br>
+Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasruhubrndsat">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vasruhubrndsat_128B,VI_ftype_VIVISI,3)<br>
+// tag : V6_vasruhubrndsat_128B<br>
+def int_hexagon_V6_vasruhubrndsat_128B :<br>
+Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasruhubrndsat_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vaslh_acc,VI_ftype_VIVISI,3)<br>
+// tag : V6_vaslh_acc<br>
+def int_hexagon_V6_vaslh_acc :<br>
+Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vaslh_acc">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vaslh_acc_128B,VI_ftype_VIVISI,3)<br>
+// tag : V6_vaslh_acc_128B<br>
+def int_hexagon_V6_vaslh_acc_128B :<br>
+Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vaslh_acc_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vasrh_acc,VI_ftype_VIVISI,3)<br>
+// tag : V6_vasrh_acc<br>
+def int_hexagon_V6_vasrh_acc :<br>
+Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrh_acc">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vasrh_acc_128B,VI_ftype_VIVISI,3)<br>
+// tag : V6_vasrh_acc_128B<br>
+def int_hexagon_V6_vasrh_acc_128B :<br>
+Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrh_acc_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vavguw,VI_ftype_VIVI,2)<br>
+// tag : V6_vavguw<br>
+def int_hexagon_V6_vavguw :<br>
+Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavguw">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vavguw_128B,VI_ftype_VIVI,2)<br>
+// tag : V6_vavguw_128B<br>
+def int_hexagon_V6_vavguw_128B :<br>
+Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavguw_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vavguwrnd,VI_ftype_VIVI,2)<br>
+// tag : V6_vavguwrnd<br>
+def int_hexagon_V6_vavguwrnd :<br>
+Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavguwrnd">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vavguwrnd_128B,VI_ftype_VIVI,2)<br>
+// tag : V6_vavguwrnd_128B<br>
+def int_hexagon_V6_vavguwrnd_128B :<br>
+Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavguwrnd_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vavgb,VI_ftype_VIVI,2)<br>
+// tag : V6_vavgb<br>
+def int_hexagon_V6_vavgb :<br>
+Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavgb">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vavgb_128B,VI_ftype_VIVI,2)<br>
+// tag : V6_vavgb_128B<br>
+def int_hexagon_V6_vavgb_128B :<br>
+Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgb_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vavgbrnd,VI_ftype_VIVI,2)<br>
+// tag : V6_vavgbrnd<br>
+def int_hexagon_V6_vavgbrnd :<br>
+Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavgbrnd">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vavgbrnd_128B,VI_ftype_VIVI,2)<br>
+// tag : V6_vavgbrnd_128B<br>
+def int_hexagon_V6_vavgbrnd_128B :<br>
+Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgbrnd_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vnavgb,VI_ftype_VIVI,2)<br>
+// tag : V6_vnavgb<br>
+def int_hexagon_V6_vnavgb :<br>
+Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vnavgb">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vnavgb_128B,VI_ftype_VIVI,2)<br>
+// tag : V6_vnavgb_128B<br>
+def int_hexagon_V6_vnavgb_128B :<br>
+Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vnavgb_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vabsb,VI_ftype_VI,1)<br>
+// tag : V6_vabsb<br>
+def int_hexagon_V6_vabsb :<br>
+Hexagon_V65_v512v512_Intrinsic<"HEXAGON_V6_vabsb">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vabsb_128B,VI_ftype_VI,1)<br>
+// tag : V6_vabsb_128B<br>
+def int_hexagon_V6_vabsb_128B :<br>
+Hexagon_V65_v1024v1024_Intrinsic<"HEXAGON_V6_vabsb_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vabsb_sat,VI_ftype_VI,1)<br>
+// tag : V6_vabsb_sat<br>
+def int_hexagon_V6_vabsb_sat :<br>
+Hexagon_V65_v512v512_Intrinsic<"HEXAGON_V6_vabsb_sat">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vabsb_sat_128B,VI_ftype_VI,1)<br>
+// tag : V6_vabsb_sat_128B<br>
+def int_hexagon_V6_vabsb_sat_128B :<br>
+Hexagon_V65_v1024v1024_Intrinsic<"HEXAGON_V6_vabsb_sat_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vmpabuu,VD_ftype_VDSI,2)<br>
+// tag : V6_vmpabuu<br>
+def int_hexagon_V6_vmpabuu :<br>
+Hexagon_V65_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpabuu">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vmpabuu_128B,VD_ftype_VDSI,2)<br>
+// tag : V6_vmpabuu_128B<br>
+def int_hexagon_V6_vmpabuu_128B :<br>
+Hexagon_V65_v2048v2048i_Intrinsic<"HEXAGON_V6_vmpabuu_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vmpabuu_acc,VD_ftype_VDVDSI,3)<br>
+// tag : V6_vmpabuu_acc<br>
+def int_hexagon_V6_vmpabuu_acc :<br>
+Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpabuu_acc">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vmpabuu_acc_128B,VD_ftype_VDVDSI,3)<br>
+// tag : V6_vmpabuu_acc_128B<br>
+def int_hexagon_V6_vmpabuu_acc_128B :<br>
+Hexagon_V65_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vmpabuu_acc_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vmpyh_acc,VD_ftype_VDVISI,3)<br>
+// tag : V6_vmpyh_acc<br>
+def int_hexagon_V6_vmpyh_acc :<br>
+Hexagon_V65_v1024v1024v512i_Intrinsic<"HEXAGON_V6_vmpyh_acc">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vmpyh_acc_128B,VD_ftype_VDVISI,3)<br>
+// tag : V6_vmpyh_acc_128B<br>
+def int_hexagon_V6_vmpyh_acc_128B :<br>
+Hexagon_V65_v2048v2048v1024i_Intrinsic<"HEXAGON_V6_vmpyh_acc_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vmpahhsat,VI_ftype_VIVIDI,3)<br>
+// tag : V6_vmpahhsat<br>
+def int_hexagon_V6_vmpahhsat :<br>
+Hexagon_V65_v512v512v512LLi_Intrinsic<"HEXAGON_V6_vmpahhsat">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vmpahhsat_128B,VI_ftype_VIVIDI,3)<br>
+// tag : V6_vmpahhsat_128B<br>
+def int_hexagon_V6_vmpahhsat_128B :<br>
+Hexagon_V65_v1024v1024v1024LLi_Intrinsic<"HEXAGON_V6_vmpahhsat_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vmpauhuhsat,VI_ftype_VIVIDI,3)<br>
+// tag : V6_vmpauhuhsat<br>
+def int_hexagon_V6_vmpauhuhsat :<br>
+Hexagon_V65_v512v512v512LLi_Intrinsic<"HEXAGON_V6_vmpauhuhsat">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vmpauhuhsat_128B,VI_ftype_VIVIDI,3)<br>
+// tag : V6_vmpauhuhsat_128B<br>
+def int_hexagon_V6_vmpauhuhsat_128B :<br>
+Hexagon_V65_v1024v1024v1024LLi_Intrinsic<"HEXAGON_V6_vmpauhuhsat_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vmpsuhuhsat,VI_ftype_VIVIDI,3)<br>
+// tag : V6_vmpsuhuhsat<br>
+def int_hexagon_V6_vmpsuhuhsat :<br>
+Hexagon_V65_v512v512v512LLi_Intrinsic<"HEXAGON_V6_vmpsuhuhsat">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vmpsuhuhsat_128B,VI_ftype_VIVIDI,3)<br>
+// tag : V6_vmpsuhuhsat_128B<br>
+def int_hexagon_V6_vmpsuhuhsat_128B :<br>
+Hexagon_V65_v1024v1024v1024LLi_Intrinsic<"HEXAGON_V6_vmpsuhuhsat_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vlut4,VI_ftype_VIDI,2)<br>
+// tag : V6_vlut4<br>
+def int_hexagon_V6_vlut4 :<br>
+Hexagon_V65_v512v512LLi_Intrinsic<"HEXAGON_V6_vlut4">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vlut4_128B,VI_ftype_VIDI,2)<br>
+// tag : V6_vlut4_128B<br>
+def int_hexagon_V6_vlut4_128B :<br>
+Hexagon_V65_v1024v1024LLi_Intrinsic<"HEXAGON_V6_vlut4_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vmpyuhe,VI_ftype_VISI,2)<br>
+// tag : V6_vmpyuhe<br>
+def int_hexagon_V6_vmpyuhe :<br>
+Hexagon_V65_v512v512i_Intrinsic<"HEXAGON_V6_vmpyuhe">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vmpyuhe_128B,VI_ftype_VISI,2)<br>
+// tag : V6_vmpyuhe_128B<br>
+def int_hexagon_V6_vmpyuhe_128B :<br>
+Hexagon_V65_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyuhe_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vmpyuhe_acc,VI_ftype_VIVISI,3)<br>
+// tag : V6_vmpyuhe_acc<br>
+def int_hexagon_V6_vmpyuhe_acc :<br>
+Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vmpyuhe_acc">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vmpyuhe_acc_128B,VI_ftype_VIVISI,3)<br>
+// tag : V6_vmpyuhe_acc_128B<br>
+def int_hexagon_V6_vmpyuhe_acc_128B :<br>
+Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyuhe_acc_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vprefixqb,VI_ftype_QV,1)<br>
+// tag : V6_vprefixqb<br>
+def int_hexagon_V6_vprefixqb :<br>
+Hexagon_V65_v512v64i_Intrinsic<"HEXAGON_V6_vprefixqb">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vprefixqb_128B,VI_ftype_QV,1)<br>
+// tag : V6_vprefixqb_128B<br>
+def int_hexagon_V6_vprefixqb_128B :<br>
+Hexagon_V65_v1024v128i_Intrinsic<"HEXAGON_V6_vprefixqb_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vprefixqh,VI_ftype_QV,1)<br>
+// tag : V6_vprefixqh<br>
+def int_hexagon_V6_vprefixqh :<br>
+Hexagon_V65_v512v64i_Intrinsic<"HEXAGON_V6_vprefixqh">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vprefixqh_128B,VI_ftype_QV,1)<br>
+// tag : V6_vprefixqh_128B<br>
+def int_hexagon_V6_vprefixqh_128B :<br>
+Hexagon_V65_v1024v128i_Intrinsic<"HEXAGON_V6_vprefixqh_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vprefixqw,VI_ftype_QV,1)<br>
+// tag : V6_vprefixqw<br>
+def int_hexagon_V6_vprefixqw :<br>
+Hexagon_V65_v512v64i_Intrinsic<"HEXAGON_V6_vprefixqw">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vprefixqw_128B,VI_ftype_QV,1)<br>
+// tag : V6_vprefixqw_128B<br>
+def int_hexagon_V6_vprefixqw_128B :<br>
+Hexagon_V65_v1024v128i_Intrinsic<"HEXAGON_V6_vprefixqw_128B">;<br>
+<br>
+<br>
+// The scatter/gather ones below will not be generated from iset.py. Make sure<br>
+// you don't overwrite these.<br>
+class Hexagon_V65_vvmemiiv512_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,<br>
+ llvm_v16i32_ty],<br>
+ [IntrArgMemOnly]>;<br>
+<br>
+class Hexagon_V65_vvmemiiv1024_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,<br>
+ llvm_v32i32_ty],<br>
+ [IntrArgMemOnly]>;<br>
+<br>
+class Hexagon_V65_vvmemiiv2048_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,<br>
+ llvm_v64i32_ty],<br>
+ [IntrArgMemOnly]>;<br>
+<br>
+class Hexagon_V65_vvmemv64iiiv512_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty,<br>
+ llvm_i32_ty,llvm_v16i32_ty],<br>
+ [IntrArgMemOnly]>;<br>
+<br>
+class Hexagon_V65_vvmemv128iiiv1024_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty,<br>
+ llvm_i32_ty,llvm_v32i32_ty],<br>
+ [IntrArgMemOnly]>;<br>
+<br>
+class Hexagon_V65_vvmemv64iiiv1024_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty,<br>
+ llvm_i32_ty,llvm_v32i32_ty],<br>
+ [IntrArgMemOnly]>;<br>
+<br>
+class Hexagon_V65_vvmemv128iiiv2048_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty,<br>
+ llvm_i32_ty,llvm_v64i32_ty],<br>
+ [IntrArgMemOnly]>;<br>
+<br>
+def int_hexagon_V6_vgathermw :<br>
+Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermw">;<br>
+<br>
+def int_hexagon_V6_vgathermw_128B :<br>
+Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermw_128B">;<br>
+<br>
+def int_hexagon_V6_vgathermh :<br>
+Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermh">;<br>
+<br>
+def int_hexagon_V6_vgathermh_128B :<br>
+Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermh_128B">;<br>
+<br>
+def int_hexagon_V6_vgathermhw :<br>
+Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermhw">;<br>
+<br>
+def int_hexagon_V6_vgathermhw_128B :<br>
+Hexagon_V65_vvmemiiv2048_Intrinsic<"HEXAGON_V6_vgathermhw_128B">;<br>
+<br>
+def int_hexagon_V6_vgathermwq :<br>
+Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermwq">;<br>
+<br>
+def int_hexagon_V6_vgathermwq_128B :<br>
+Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermwq_128B">;<br>
+<br>
+def int_hexagon_V6_vgathermhq :<br>
+Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermhq">;<br>
+<br>
+def int_hexagon_V6_vgathermhq_128B :<br>
+Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhq_128B">;<br>
+<br>
+def int_hexagon_V6_vgathermhwq :<br>
+Hexagon_V65_vvmemv64iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhwq">;<br>
+<br>
+def int_hexagon_V6_vgathermhwq_128B :<br>
+Hexagon_V65_vvmemv128iiiv2048_Intrinsic<"HEXAGON_V6_vgathermhwq_128B">;<br>
+<br>
+class Hexagon_V65_viiv512v512_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [], [llvm_i32_ty,llvm_i32_ty,<br>
+ llvm_v16i32_ty,llvm_v16i32_ty],<br>
+ [IntrWriteMem]>;<br>
+<br>
+class Hexagon_V65_viiv1024v1024_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [], [llvm_i32_ty,llvm_i32_ty,<br>
+ llvm_v32i32_ty,llvm_v32i32_ty],<br>
+ [IntrWriteMem]>;<br>
+<br>
+class Hexagon_V65_vv64iiiv512v512_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [], [llvm_v512i1_ty,llvm_i32_ty,<br>
+ llvm_i32_ty,llvm_v16i32_ty,<br>
+ llvm_v16i32_ty],<br>
+ [IntrWriteMem]>;<br>
+<br>
+class Hexagon_V65_vv128iiiv1024v1024_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [], [llvm_v1024i1_ty,llvm_i32_ty,<br>
+ llvm_i32_ty,llvm_v32i32_ty,<br>
+ llvm_v32i32_ty],<br>
+ [IntrWriteMem]>;<br>
+<br>
+class Hexagon_V65_viiv1024v512_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [], [llvm_i32_ty,llvm_i32_ty,<br>
+ llvm_v32i32_ty,llvm_v16i32_ty],<br>
+ [IntrWriteMem]>;<br>
+<br>
+class Hexagon_V65_viiv2048v1024_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [], [llvm_i32_ty,llvm_i32_ty,<br>
+ llvm_v64i32_ty,llvm_v32i32_ty],<br>
+ [IntrWriteMem]>;<br>
+<br>
+class Hexagon_V65_vv64iiiv1024v512_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [], [llvm_v512i1_ty,llvm_i32_ty,<br>
+ llvm_i32_ty,llvm_v32i32_ty,<br>
+ llvm_v16i32_ty],<br>
+ [IntrWriteMem]>;<br>
+<br>
+class Hexagon_V65_vv128iiiv2048v1024_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [], [llvm_v1024i1_ty,llvm_i32_ty,<br>
+ llvm_i32_ty,llvm_v64i32_ty,<br>
+ llvm_v32i32_ty],<br>
+ [IntrWriteMem]>;<br>
+<br>
+class Hexagon_V65_v2048_Intrinsic<string GCCIntSuffix><br>
+ : Hexagon_Intrinsic<GCCIntSuffix,<br>
+ [llvm_v64i32_ty], [],<br>
+ [IntrNoMem]>;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vscattermw,v_ftype_SISIVIVI,4)<br>
+// tag : V6_vscattermw<br>
+def int_hexagon_V6_vscattermw :<br>
+Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vscattermw_128B,v_ftype_SISIVIVI,4)<br>
+// tag : V6_vscattermw_128B<br>
+def int_hexagon_V6_vscattermw_128B :<br>
+Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vscattermh,v_ftype_SISIVIVI,4)<br>
+// tag : V6_vscattermh<br>
+def int_hexagon_V6_vscattermh :<br>
+Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vscattermh_128B,v_ftype_SISIVIVI,4)<br>
+// tag : V6_vscattermh_128B<br>
+def int_hexagon_V6_vscattermh_128B :<br>
+Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vscattermw_add,v_ftype_SISIVIVI,4)<br>
+// tag : V6_vscattermw_add<br>
+def int_hexagon_V6_vscattermw_add :<br>
+Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw_add">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vscattermw_add_128B,v_ftype_SISIVIVI,4)<br>
+// tag : V6_vscattermw_add_128B<br>
+def int_hexagon_V6_vscattermw_add_128B :<br>
+Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_add_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vscattermh_add,v_ftype_SISIVIVI,4)<br>
+// tag : V6_vscattermh_add<br>
+def int_hexagon_V6_vscattermh_add :<br>
+Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh_add">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vscattermh_add_128B,v_ftype_SISIVIVI,4)<br>
+// tag : V6_vscattermh_add_128B<br>
+def int_hexagon_V6_vscattermh_add_128B :<br>
+Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_add_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vscattermwq,v_ftype_QVSISIVIVI,5)<br>
+// tag : V6_vscattermwq<br>
+def int_hexagon_V6_vscattermwq :<br>
+Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermwq">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vscattermwq_128B,v_ftype_QVSISIVIVI,5)<br>
+// tag : V6_vscattermwq_128B<br>
+def int_hexagon_V6_vscattermwq_128B :<br>
+Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermwq_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vscattermhq,v_ftype_QVSISIVIVI,5)<br>
+// tag : V6_vscattermhq<br>
+def int_hexagon_V6_vscattermhq :<br>
+Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermhq">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vscattermhq_128B,v_ftype_QVSISIVIVI,5)<br>
+// tag : V6_vscattermhq_128B<br>
+def int_hexagon_V6_vscattermhq_128B :<br>
+Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermhq_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vscattermhw,v_ftype_SISIVDVI,4)<br>
+// tag : V6_vscattermhw<br>
+def int_hexagon_V6_vscattermhw :<br>
+Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vscattermhw_128B,v_ftype_SISIVDVI,4)<br>
+// tag : V6_vscattermhw_128B<br>
+def int_hexagon_V6_vscattermhw_128B :<br>
+Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vscattermhwq,v_ftype_QVSISIVDVI,5)<br>
+// tag : V6_vscattermhwq<br>
+def int_hexagon_V6_vscattermhwq :<br>
+Hexagon_V65_vv64iiiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhwq">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vscattermhwq_128B,v_ftype_QVSISIVDVI,5)<br>
+// tag : V6_vscattermhwq_128B<br>
+def int_hexagon_V6_vscattermhwq_128B :<br>
+Hexagon_V65_vv128iiiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhwq_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vscattermhw_add,v_ftype_SISIVDVI,4)<br>
+// tag : V6_vscattermhw_add<br>
+def int_hexagon_V6_vscattermhw_add :<br>
+Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw_add">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vscattermhw_add_128B,v_ftype_SISIVDVI,4)<br>
+// tag : V6_vscattermhw_add_128B<br>
+def int_hexagon_V6_vscattermhw_add_128B :<br>
+Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_add_128B">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vdd0,VD_ftype_,0)<br>
+// tag : V6_vdd0<br>
+def int_hexagon_V6_vdd0 :<br>
+Hexagon_v1024_Intrinsic<"HEXAGON_V6_vdd0">;<br>
+<br>
+//<br>
+// BUILTIN_INFO(HEXAGON.V6_vdd0_128B,VD_ftype_,0)<br>
+// tag : V6_vdd0_128B<br>
+def int_hexagon_V6_vdd0_128B :<br>
+Hexagon_V65_v2048_Intrinsic<"HEXAGON_V6_vdd0_128B">;<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp?rev=320404&r1=320403&r2=320404&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp?rev=320404&r1=320403&r2=320404&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp Mon Dec 11 10:57:54 2017<br>
@@ -47,6 +47,7 @@<br>
#include "llvm/Support/Format.h"<br>
#include "llvm/Support/MathExtras.h"<br>
#include "llvm/Support/SMLoc.h"<br>
+#include "llvm/Support/SourceMgr.h"<br>
#include "llvm/Support/TargetRegistry.h"<br>
#include "llvm/Support/raw_ostream.h"<br>
#include <algorithm><br>
@@ -60,9 +61,6 @@<br>
<br>
using namespace llvm;<br>
<br>
-static cl::opt<bool> EnableFutureRegs("mfuture-regs",<br>
- cl::desc("Enable future registers"));<br>
-<br>
static cl::opt<bool> WarnMissingParenthesis(<br>
"mwarn-missing-parenthesis",<br>
cl::desc("Warn for missing parenthesis around predicate registers"),<br>
@@ -95,12 +93,20 @@ class HexagonAsmParser : public MCTarget<br>
}<br>
<br>
MCAsmParser &Parser;<br>
- MCAssembler *Assembler;<br>
MCInst MCB;<br>
bool InBrackets;<br>
<br>
MCAsmParser &getParser() const { return Parser; }<br>
- MCAssembler *getAssembler() const { return Assembler; }<br>
+ MCAssembler *getAssembler() const {<br>
+ MCAssembler *Assembler = nullptr;<br>
+ // FIXME: need better way to detect AsmStreamer (upstream removed getKind())<br>
+ if (!Parser.getStreamer().hasRawTextSupport()) {<br>
+ MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer());<br>
+ Assembler = &MES->getAssembler();<br>
+ }<br>
+ return Assembler;<br>
+ }<br>
+<br>
MCAsmLexer &getLexer() const { return Parser.getLexer(); }<br>
<br>
bool equalIsAsmAssignment() override { return false; }<br>
@@ -123,7 +129,7 @@ class HexagonAsmParser : public MCTarget<br>
bool matchOneInstruction(MCInst &MCB, SMLoc IDLoc,<br>
OperandVector &InstOperands, uint64_t &ErrorInfo,<br>
bool MatchingInlineAsm);<br>
-<br>
+ void eatToEndOfPacket();<br>
bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,<br>
OperandVector &Operands, MCStreamer &Out,<br>
uint64_t &ErrorInfo,<br>
@@ -155,17 +161,11 @@ public:<br>
HexagonAsmParser(const MCSubtargetInfo &_STI, MCAsmParser &_Parser,<br>
const MCInstrInfo &MII, const MCTargetOptions &Options)<br>
: MCTargetAsmParser(Options, _STI, MII), Parser(_Parser),<br>
- MCB(HexagonMCInstrInfo::createBundle()), InBrackets(false) {<br>
+ InBrackets(false) {<br>
+ MCB.setOpcode(Hexagon::BUNDLE);<br>
setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));<br>
<br>
MCAsmParserExtension::Initialize(_Parser);<br>
-<br>
- Assembler = nullptr;<br>
- // FIXME: need better way to detect AsmStreamer (upstream removed getKind())<br>
- if (!Parser.getStreamer().hasRawTextSupport()) {<br>
- MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer());<br>
- Assembler = &MES->getAssembler();<br>
- }<br>
}<br>
<br>
bool splitIdentifier(OperandVector &Operands);<br>
@@ -190,6 +190,7 @@ public:<br>
/// instruction.<br>
struct HexagonOperand : public MCParsedAsmOperand {<br>
enum KindTy { Token, Immediate, Register } Kind;<br>
+ MCContext &Context;<br>
<br>
SMLoc StartLoc, EndLoc;<br>
<br>
@@ -216,10 +217,12 @@ struct HexagonOperand : public MCParsedA<br>
struct ImmTy Imm;<br>
};<br>
<br>
- HexagonOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}<br>
+ HexagonOperand(KindTy K, MCContext &Context)<br>
+ : MCParsedAsmOperand(), Kind(K), Context(Context) {}<br>
<br>
public:<br>
- HexagonOperand(const HexagonOperand &o) : MCParsedAsmOperand() {<br>
+ HexagonOperand(const HexagonOperand &o)<br>
+ : MCParsedAsmOperand(), Context(o.Context) {<br>
Kind = o.Kind;<br>
StartLoc = o.StartLoc;<br>
EndLoc = o.EndLoc;<br>
@@ -392,9 +395,13 @@ public:<br>
return;<br>
}<br>
int64_t Extended = SignExtend64(Value, 32);<br>
+ HexagonMCExpr *NewExpr = HexagonMCExpr::create(<br>
+ MCConstantExpr::create(Extended, Context), Context);<br>
if ((Extended < 0) != (Value < 0))<br>
- Expr->setSignMismatch();<br>
- Inst.addOperand(MCOperand::createExpr(Expr));<br>
+ NewExpr->setSignMismatch();<br>
+ NewExpr->setMustExtend(Expr->mustExtend());<br>
+ NewExpr->setMustNotExtend(Expr->mustNotExtend());<br>
+ Inst.addOperand(MCOperand::createExpr(NewExpr));<br>
}<br>
<br>
void addn1ConstOperands(MCInst &Inst, unsigned N) const {<br>
@@ -408,8 +415,9 @@ public:<br>
<br>
void print(raw_ostream &OS) const override;<br>
<br>
- static std::unique_ptr<HexagonOperand> CreateToken(StringRef Str, SMLoc S) {<br>
- HexagonOperand *Op = new HexagonOperand(Token);<br>
+ static std::unique_ptr<HexagonOperand> CreateToken(MCContext &Context,<br>
+ StringRef Str, SMLoc S) {<br>
+ HexagonOperand *Op = new HexagonOperand(Token, Context);<br>
Op->Tok.Data = Str.data();<br>
Op->Tok.Length = Str.size();<br>
Op->StartLoc = S;<br>
@@ -417,18 +425,18 @@ public:<br>
return std::unique_ptr<HexagonOperand>(Op);<br>
}<br>
<br>
- static std::unique_ptr<HexagonOperand> CreateReg(unsigned RegNum, SMLoc S,<br>
- SMLoc E) {<br>
- HexagonOperand *Op = new HexagonOperand(Register);<br>
+ static std::unique_ptr<HexagonOperand><br>
+ CreateReg(MCContext &Context, unsigned RegNum, SMLoc S, SMLoc E) {<br>
+ HexagonOperand *Op = new HexagonOperand(Register, Context);<br>
Op->Reg.RegNum = RegNum;<br>
Op->StartLoc = S;<br>
Op->EndLoc = E;<br>
return std::unique_ptr<HexagonOperand>(Op);<br>
}<br>
<br>
- static std::unique_ptr<HexagonOperand> CreateImm(const MCExpr *Val, SMLoc S,<br>
- SMLoc E) {<br>
- HexagonOperand *Op = new HexagonOperand(Immediate);<br>
+ static std::unique_ptr<HexagonOperand><br>
+ CreateImm(MCContext &Context, const MCExpr *Val, SMLoc S, SMLoc E) {<br>
+ HexagonOperand *Op = new HexagonOperand(Immediate, Context);<br>
Op->Imm.Val = Val;<br>
Op->StartLoc = S;<br>
Op->EndLoc = E;<br>
@@ -480,8 +488,8 @@ bool HexagonAsmParser::finishBundle(SMLo<br>
// 4 or less we have a packet that is too big.<br>
if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE) {<br>
Error(IDLoc, "invalid instruction packet: out of slots");<br>
- return true; // Error<br>
}<br>
+ return true; // Error<br>
}<br>
<br>
return false; // No error<br>
@@ -493,13 +501,23 @@ bool HexagonAsmParser::matchBundleOption<br>
if (!Parser.getTok().is(AsmToken::Colon))<br>
return false;<br>
Lex();<br>
+ char const *MemNoShuffMsg =<br>
+ "invalid instruction packet: mem_noshuf specifier not "<br>
+ "supported with this architecture";<br>
StringRef Option = Parser.getTok().getString();<br>
+ auto IDLoc = Parser.getTok().getLoc();<br>
if (Option.compare_lower("endloop0") == 0)<br>
HexagonMCInstrInfo::setInnerLoop(MCB);<br>
else if (Option.compare_lower("endloop1") == 0)<br>
HexagonMCInstrInfo::setOuterLoop(MCB);<br>
+ else if (Option.compare_lower("mem_noshuf") == 0)<br>
+ if (getSTI().getFeatureBits()[Hexagon::FeatureMemNoShuf])<br>
+ HexagonMCInstrInfo::setMemReorderDisabled(MCB);<br>
+ else<br>
+ return getParser().Error(IDLoc, MemNoShuffMsg);<br>
else<br>
- return true;<br>
+ return getParser().Error(IDLoc, llvm::Twine("'") + Option +<br>
+ "' is not a valid bundle option");<br>
Lex();<br>
}<br>
}<br>
@@ -512,13 +530,13 @@ void HexagonAsmParser::canonicalizeImmed<br>
NewInst.setOpcode(MCI.getOpcode());<br>
for (MCOperand &I : MCI)<br>
if (I.isImm()) {<br>
- int64_t Value (I.getImm());<br>
+ int64_t Value(I.getImm());<br>
NewInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(<br>
MCConstantExpr::create(Value, getContext()), getContext())));<br>
} else {<br>
if (I.isExpr() && cast<HexagonMCExpr>(I.getExpr())->signMismatch() &&<br>
WarnSignedMismatch)<br>
- Warning (MCI.getLoc(), "Signed/Unsigned mismatch");<br>
+ Warning(MCI.getLoc(), "Signed/Unsigned mismatch");<br>
NewInst.addOperand(I);<br>
}<br>
MCI = NewInst;<br>
@@ -572,6 +590,15 @@ bool HexagonAsmParser::matchOneInstructi<br>
llvm_unreachable("Implement any new match types added!");<br>
}<br>
<br>
+void HexagonAsmParser::eatToEndOfPacket() {<br>
+ assert(InBrackets);<br>
+ MCAsmLexer &Lexer = getLexer();<br>
+ while (!Lexer.is(AsmToken::RCurly))<br>
+ Lexer.Lex();<br>
+ Lexer.Lex();<br>
+ InBrackets = false;<br>
+}<br>
+<br>
bool HexagonAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,<br>
OperandVector &Operands,<br>
MCStreamer &Out,<br>
@@ -586,6 +613,7 @@ bool HexagonAsmParser::MatchAndEmitInstr<br>
assert(Operands.size() == 1 && "Brackets should be by themselves");<br>
if (InBrackets) {<br>
getParser().Error(IDLoc, "Already in a packet");<br>
+ InBrackets = false;<br>
return true;<br>
}<br>
InBrackets = true;<br>
@@ -604,8 +632,11 @@ bool HexagonAsmParser::MatchAndEmitInstr<br>
}<br>
MCInst *SubInst = new (getParser().getContext()) MCInst;<br>
if (matchOneInstruction(*SubInst, IDLoc, Operands, ErrorInfo,<br>
- MatchingInlineAsm))<br>
+ MatchingInlineAsm)) {<br>
+ if (InBrackets)<br>
+ eatToEndOfPacket();<br>
return true;<br>
+ }<br>
HexagonMCInstrInfo::extendIfNeeded(<br>
getParser().getContext(), MII, MCB, *SubInst);<br>
MCB.addOperand(MCOperand::createInst(SubInst));<br>
@@ -853,10 +884,11 @@ bool HexagonAsmParser::splitIdentifier(O<br>
do {<br>
std::pair<StringRef, StringRef> HeadTail = String.split('.');<br>
if (!HeadTail.first.empty())<br>
- Operands.push_back(HexagonOperand::CreateToken(HeadTail.first, Loc));<br>
+ Operands.push_back(<br>
+ HexagonOperand::CreateToken(getContext(), HeadTail.first, Loc));<br>
if (!HeadTail.second.empty())<br>
Operands.push_back(HexagonOperand::CreateToken(<br>
- String.substr(HeadTail.first.size(), 1), Loc));<br>
+ getContext(), String.substr(HeadTail.first.size(), 1), Loc));<br>
String = HeadTail.second;<br>
} while (!String.empty());<br>
return false;<br>
@@ -878,38 +910,43 @@ bool HexagonAsmParser::parseOperand(Oper<br>
case Hexagon::P3:<br>
if (previousEqual(Operands, 0, "if")) {<br>
if (WarnMissingParenthesis)<br>
- Warning (Begin, "Missing parenthesis around predicate register");<br>
+ Warning(Begin, "Missing parenthesis around predicate register");<br>
static char const *LParen = "(";<br>
static char const *RParen = ")";<br>
- Operands.push_back(HexagonOperand::CreateToken(LParen, Begin));<br>
- Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End));<br>
+ Operands.push_back(<br>
+ HexagonOperand::CreateToken(getContext(), LParen, Begin));<br>
+ Operands.push_back(<br>
+ HexagonOperand::CreateReg(getContext(), Register, Begin, End));<br>
const AsmToken &MaybeDotNew = Lexer.getTok();<br>
if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&<br>
MaybeDotNew.getString().equals_lower(".new"))<br>
splitIdentifier(Operands);<br>
- Operands.push_back(HexagonOperand::CreateToken(RParen, Begin));<br>
+ Operands.push_back(<br>
+ HexagonOperand::CreateToken(getContext(), RParen, Begin));<br>
return false;<br>
}<br>
if (previousEqual(Operands, 0, "!") &&<br>
previousEqual(Operands, 1, "if")) {<br>
if (WarnMissingParenthesis)<br>
- Warning (Begin, "Missing parenthesis around predicate register");<br>
+ Warning(Begin, "Missing parenthesis around predicate register");<br>
static char const *LParen = "(";<br>
static char const *RParen = ")";<br>
- Operands.insert(Operands.end () - 1,<br>
- HexagonOperand::CreateToken(LParen, Begin));<br>
- Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End));<br>
+ Operands.insert(Operands.end() - 1, HexagonOperand::CreateToken(<br>
+ getContext(), LParen, Begin));<br>
+ Operands.push_back(<br>
+ HexagonOperand::CreateReg(getContext(), Register, Begin, End));<br>
const AsmToken &MaybeDotNew = Lexer.getTok();<br>
if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&<br>
MaybeDotNew.getString().equals_lower(".new"))<br>
splitIdentifier(Operands);<br>
- Operands.push_back(HexagonOperand::CreateToken(RParen, Begin));<br>
+ Operands.push_back(<br>
+ HexagonOperand::CreateToken(getContext(), RParen, Begin));<br>
return false;<br>
}<br>
break;<br>
}<br>
- Operands.push_back(HexagonOperand::CreateReg(<br>
- Register, Begin, End));<br>
+ Operands.push_back(<br>
+ HexagonOperand::CreateReg(getContext(), Register, Begin, End));<br>
return false;<br>
}<br>
return splitIdentifier(Operands);<br>
@@ -931,10 +968,9 @@ bool HexagonAsmParser::isLabel(AsmToken<br>
return true;<br>
if (!matchRegister(String.lower()))<br>
return true;<br>
- (void)Second;<br>
assert(Second.is(AsmToken::Colon));<br>
- StringRef Raw (String.data(), Third.getString().data() - String.data() +<br>
- Third.getString().size());<br>
+ StringRef Raw(String.data(), Third.getString().data() - String.data() +<br>
+ Third.getString().size());<br>
std::string Collapsed = Raw;<br>
Collapsed.erase(llvm::remove_if(Collapsed, isspace), Collapsed.end());<br>
StringRef Whole = Collapsed;<br>
@@ -944,7 +980,8 @@ bool HexagonAsmParser::isLabel(AsmToken<br>
return false;<br>
}<br>
<br>
-bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious, SMLoc &Loc) {<br>
+bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious,<br>
+ SMLoc &Loc) {<br>
if (!Contigious && ErrorNoncontigiousRegister) {<br>
Error(Loc, "Register name is not contigious");<br>
return true;<br>
@@ -954,7 +991,8 @@ bool HexagonAsmParser::handleNoncontigio<br>
return false;<br>
}<br>
<br>
-bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {<br>
+bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,<br>
+ SMLoc &EndLoc) {<br>
MCAsmLexer &Lexer = getLexer();<br>
StartLoc = getLexer().getLoc();<br>
SmallVector<AsmToken, 5> Lookahead;<br>
@@ -963,19 +1001,19 @@ bool HexagonAsmParser::ParseRegister(uns<br>
bool NeededWorkaround = false;<br>
while (Again) {<br>
AsmToken const &Token = Lexer.getTok();<br>
- RawString = StringRef(RawString.data(),<br>
- Token.getString().data() - RawString.data () +<br>
- Token.getString().size());<br>
+ RawString = StringRef(RawString.data(), Token.getString().data() -<br>
+ RawString.data() +<br>
+ Token.getString().size());<br>
Lookahead.push_back(Token);<br>
Lexer.Lex();<br>
bool Contigious = Lexer.getTok().getString().data() ==<br>
Lookahead.back().getString().data() +<br>
- Lookahead.back().getString().size();<br>
+ Lookahead.back().getString().size();<br>
bool Type = Lexer.is(AsmToken::Identifier) || Lexer.is(AsmToken::Dot) ||<br>
Lexer.is(AsmToken::Integer) || Lexer.is(AsmToken::Real) ||<br>
Lexer.is(AsmToken::Colon);<br>
- bool Workaround = Lexer.is(AsmToken::Colon) ||<br>
- Lookahead.back().is(AsmToken::Colon);<br>
+ bool Workaround =<br>
+ Lexer.is(AsmToken::Colon) || Lookahead.back().is(AsmToken::Colon);<br>
Again = (Contigious && Type) || (Workaround && Type);<br>
NeededWorkaround = NeededWorkaround || (Again && !(Contigious && Type));<br>
}<br>
@@ -1005,10 +1043,10 @@ bool HexagonAsmParser::ParseRegister(uns<br>
std::pair<StringRef, StringRef> ColonSplit = StringRef(FullString).split(':');<br>
unsigned ColonReg = matchRegister(ColonSplit.first.lower());<br>
if (ColonReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {<br>
- Lexer.UnLex(Lookahead.back());<br>
- Lookahead.pop_back();<br>
- Lexer.UnLex(Lookahead.back());<br>
- Lookahead.pop_back();<br>
+ do {<br>
+ Lexer.UnLex(Lookahead.back());<br>
+ Lookahead.pop_back();<br>
+ } while (!Lookahead.empty () && !Lexer.is(AsmToken::Colon));<br>
RegNo = ColonReg;<br>
EndLoc = Lexer.getLoc();<br>
if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))<br>
@@ -1036,19 +1074,18 @@ bool HexagonAsmParser::implicitExpressio<br>
return false;<br>
}<br>
<br>
-bool HexagonAsmParser::parseExpression(MCExpr const *& Expr) {<br>
+bool HexagonAsmParser::parseExpression(MCExpr const *&Expr) {<br>
SmallVector<AsmToken, 4> Tokens;<br>
MCAsmLexer &Lexer = getLexer();<br>
bool Done = false;<br>
- static char const * Comma = ",";<br>
+ static char const *Comma = ",";<br>
do {<br>
- Tokens.emplace_back (Lexer.getTok());<br>
+ Tokens.emplace_back(Lexer.getTok());<br>
Lex();<br>
- switch (Tokens.back().getKind())<br>
- {<br>
+ switch (Tokens.back().getKind()) {<br>
case AsmToken::TokenKind::Hash:<br>
- if (Tokens.size () > 1)<br>
- if ((Tokens.end () - 2)->getKind() == AsmToken::TokenKind::Plus) {<br>
+ if (Tokens.size() > 1)<br>
+ if ((Tokens.end() - 2)->getKind() == AsmToken::TokenKind::Plus) {<br>
Tokens.insert(Tokens.end() - 2,<br>
AsmToken(AsmToken::TokenKind::Comma, Comma));<br>
Done = true;<br>
@@ -1067,7 +1104,8 @@ bool HexagonAsmParser::parseExpression(M<br>
Lexer.UnLex(Tokens.back());<br>
Tokens.pop_back();<br>
}<br>
- return getParser().parseExpression(Expr);<br>
+ SMLoc Loc = Lexer.getLoc();<br>
+ return getParser().parseExpression(Expr, Loc);<br>
}<br>
<br>
bool HexagonAsmParser::parseExpressionOrOperand(OperandVector &Operands) {<br>
@@ -1078,7 +1116,8 @@ bool HexagonAsmParser::parseExpressionOr<br>
bool Error = parseExpression(Expr);<br>
Expr = HexagonMCExpr::create(Expr, getContext());<br>
if (!Error)<br>
- Operands.push_back(HexagonOperand::CreateImm(Expr, Loc, Loc));<br>
+ Operands.push_back(<br>
+ HexagonOperand::CreateImm(getContext(), Expr, Loc, Loc));<br>
return Error;<br>
}<br>
return parseOperand(Operands);<br>
@@ -1091,6 +1130,7 @@ bool HexagonAsmParser::parseInstruction(<br>
while (true) {<br>
AsmToken const &Token = Parser.getTok();<br>
switch (Token.getKind()) {<br>
+ case AsmToken::Eof:<br>
case AsmToken::EndOfStatement: {<br>
Lex();<br>
return false;<br>
@@ -1098,15 +1138,15 @@ bool HexagonAsmParser::parseInstruction(<br>
case AsmToken::LCurly: {<br>
if (!Operands.empty())<br>
return true;<br>
- Operands.push_back(<br>
- HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));<br>
+ Operands.push_back(HexagonOperand::CreateToken(<br>
+ getContext(), Token.getString(), Token.getLoc()));<br>
Lex();<br>
return false;<br>
}<br>
case AsmToken::RCurly: {<br>
if (Operands.empty()) {<br>
- Operands.push_back(<br>
- HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));<br>
+ Operands.push_back(HexagonOperand::CreateToken(<br>
+ getContext(), Token.getString(), Token.getLoc()));<br>
Lex();<br>
}<br>
return false;<br>
@@ -1122,9 +1162,9 @@ bool HexagonAsmParser::parseInstruction(<br>
case AsmToken::LessEqual:<br>
case AsmToken::LessLess: {<br>
Operands.push_back(HexagonOperand::CreateToken(<br>
- Token.getString().substr(0, 1), Token.getLoc()));<br>
+ getContext(), Token.getString().substr(0, 1), Token.getLoc()));<br>
Operands.push_back(HexagonOperand::CreateToken(<br>
- Token.getString().substr(1, 1), Token.getLoc()));<br>
+ getContext(), Token.getString().substr(1, 1), Token.getLoc()));<br>
Lex();<br>
continue;<br>
}<br>
@@ -1133,8 +1173,8 @@ bool HexagonAsmParser::parseInstruction(<br>
bool ImplicitExpression = implicitExpressionLocation(Operands);<br>
SMLoc ExprLoc = Lexer.getLoc();<br>
if (!ImplicitExpression)<br>
- Operands.push_back(<br>
- HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));<br>
+ Operands.push_back(HexagonOperand::CreateToken(<br>
+ getContext(), Token.getString(), Token.getLoc()));<br>
Lex();<br>
bool MustExtend = false;<br>
bool HiOnly = false;<br>
@@ -1171,16 +1211,15 @@ bool HexagonAsmParser::parseInstruction(<br>
if (Expr->evaluateAsAbsolute(Value)) {<br>
if (HiOnly)<br>
Expr = MCBinaryExpr::createLShr(<br>
- Expr, MCConstantExpr::create(16, Context), Context);<br>
+ Expr, MCConstantExpr::create(16, Context), Context);<br>
if (HiOnly || LoOnly)<br>
- Expr = MCBinaryExpr::createAnd(Expr,<br>
- MCConstantExpr::create(0xffff, Context),<br>
- Context);<br>
+ Expr = MCBinaryExpr::createAnd(<br>
+ Expr, MCConstantExpr::create(0xffff, Context), Context);<br>
} else {<br>
MCValue Value;<br>
if (Expr->evaluateAsRelocatable(Value, nullptr, nullptr)) {<br>
if (!Value.isAbsolute()) {<br>
- switch(Value.getAccessVariant()) {<br>
+ switch (Value.getAccessVariant()) {<br>
case MCSymbolRefExpr::VariantKind::VK_TPREL:<br>
case MCSymbolRefExpr::VariantKind::VK_DTPREL:<br>
// Don't lazy extend these expression variants<br>
@@ -1196,7 +1235,7 @@ bool HexagonAsmParser::parseInstruction(<br>
HexagonMCInstrInfo::setMustNotExtend(*Expr, MustNotExtend);<br>
HexagonMCInstrInfo::setMustExtend(*Expr, MustExtend);<br>
std::unique_ptr<HexagonOperand> Operand =<br>
- HexagonOperand::CreateImm(Expr, ExprLoc, ExprLoc);<br>
+ HexagonOperand::CreateImm(getContext(), Expr, ExprLoc, ExprLoc);<br>
Operands.push_back(std::move(Operand));<br>
continue;<br>
}<br>
@@ -1209,15 +1248,14 @@ bool HexagonAsmParser::parseInstruction(<br>
}<br>
<br>
bool HexagonAsmParser::ParseInstruction(ParseInstructionInfo &Info,<br>
- StringRef Name,<br>
- AsmToken ID,<br>
+ StringRef Name, AsmToken ID,<br>
OperandVector &Operands) {<br>
getLexer().UnLex(ID);<br>
return parseInstruction(Operands);<br>
}<br>
<br>
-static MCInst makeCombineInst(int opCode, MCOperand &Rdd,<br>
- MCOperand &MO1, MCOperand &MO2) {<br>
+static MCInst makeCombineInst(int opCode, MCOperand &Rdd, MCOperand &MO1,<br>
+ MCOperand &MO2) {<br>
MCInst TmpInst;<br>
TmpInst.setOpcode(opCode);<br>
TmpInst.addOperand(Rdd);<br>
@@ -1286,6 +1324,13 @@ int HexagonAsmParser::processInstruction<br>
bool is32bit = false; // used to distinguish between CONST32 and CONST64<br>
switch (Inst.getOpcode()) {<br>
default:<br>
+ if (HexagonMCInstrInfo::getDesc(MII, Inst).isPseudo()) {<br>
+ SMDiagnostic Diag = getSourceManager().GetMessage(<br>
+</blockquote></div></div></div>