[PATCH] D44612: [X86] Generalize schedule classes to support multiple stages

[Clement Courbet via Phabricator via llvm-commits]

courbet accepted this revision.
courbet added inline comments.
This revision is now accepted and ready to land.


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Comment at: lib/Target/X86/X86SchedBroadwell.td:108
+defm : BWWriteResPair<WriteIDiv, [BWPort0, BWDivider], 25, [1, 10]>;
 def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
 
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RKSimon wrote:
> courbet wrote:
> > The default value on Res will create a inconsistent values ExePorts=[] ResourceCycles=[1]. 
> This patch only affects the classes that use BWWriteResPair (and equivalents on other targets) - WriteIMulH doesn't have a Ld equivalent so uses the 'raw' WriteRes - its not affected by this change.
Oops. I scanned the file quickly to show an example for my comment on line 83. Please ignore this one, but the comment still holds, there's nothing that prevents forgetting overriding this when  ResourceCycles when providing two resources.
Arguably this should be a warning in tablegen, I've created PR36797 for this, so feel free to ignore these two comments.


Repository:
  rL LLVM

https://reviews.llvm.org/D44612