[PATCH] D44612: [X86] Generalize schedule classes to support multiple stages

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: lib/Target/X86/X86SchedBroadwell.td:108
+defm : BWWriteResPair<WriteIDiv, [BWPort0, BWDivider], 25, [1, 10]>;
 def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
 
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courbet wrote:
> The default value on Res will create a inconsistent values ExePorts=[] ResourceCycles=[1]. 
This patch only affects the classes that use BWWriteResPair (and equivalents on other targets) - WriteIMulH doesn't have a Ld equivalent so uses the 'raw' WriteRes - its not affected by this change.


Repository:
  rL LLVM

https://reviews.llvm.org/D44612