[PATCH] D44612: [X86] Generalize schedule classes to support multiple stages

[Clement Courbet via Phabricator via llvm-commits]

courbet added inline comments.


================
Comment at: lib/Target/X86/X86SchedBroadwell.td:83
+                          list<ProcResourceKind> ExePorts,
+                          int Lat, list<int> Res = [1], int UOps = 1> {
   // Register variant is using a single cycle on ExePort.
----------------
I think making Res explicit would be safer (see my comment on line 108).


================
Comment at: lib/Target/X86/X86SchedBroadwell.td:108
+defm : BWWriteResPair<WriteIDiv, [BWPort0, BWDivider], 25, [1, 10]>;
 def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
 
----------------
The default value on Res will create a inconsistent values ExePorts=[] ResourceCycles=[1]. 


Repository:
  rL LLVM

https://reviews.llvm.org/D44612