[PATCH] D43267: MIRParser: Accept overloaded intrinsic names w/o type suffixes

[Roman Tereshin via Phabricator via llvm-commits]

rtereshin marked 4 inline comments as done.
rtereshin added inline comments.


================
Comment at: test/CodeGen/MIR/AArch64/print-parse-overloaded-intrinsics.mir:1-3
+# RUN: llc -mtriple aarch64-- -run-pass irtranslator -simplify-mir %s -o - \
+# RUN:   -verify-machineinstrs | llc -mtriple aarch64-- -run-pass legalizer \
+# RUN:   -simplify-mir -x mir -o - -verify-machineinstrs | FileCheck %s
----------------
bogner wrote:
> It might be easier to tell what went wrong on failures if we output to a temporary file (ie %t) instead of doing this all in a single pipeline.
Sure! I'm changing the RUN lines to:
```
# RUN: llc -mtriple aarch64-- -run-pass irtranslator -simplify-mir %s -o %t \
# RUN:   -verify-machineinstrs; llc -mtriple aarch64-- -run-pass legalizer \
# RUN:   -simplify-mir %t -x mir -o - -verify-machineinstrs | FileCheck %s
```


================
Comment at: test/CodeGen/MIR/AArch64/print-parse-overloaded-intrinsics.mir:9-24
+--- |
+  define i32 @int_aarch64_sdiv(i32 %a, i32 %b) nounwind readnone ssp {
+  ; CHECK-LABEL: name: int_aarch64_sdiv
+  ; CHECK: liveins: $w0, $w1
+  ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+  ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+  ; CHECK: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.sdiv), [[COPY]](s32), [[COPY1]](s32)
----------------
bogner wrote:
> I guess it makes sense since this is a test for the mir parser, but it's a bit odd to have a mir file that only consists of llvm ir.
Apparently, `-run-pass` command line option isn't defined for IR files, `llc` fails like follows:
```
llc: run-pass is for .mir file only.
```
as discussed offline.

We should probably change that at some point, as well as make it possible to run IR-to-IR passes that are ran by `llc` anyway separately, in `opt` manner. Not to encourage people adding more IR-to-IR passes into `llc`'s pipeline, but to make it easier to test and troubleshoot.


Repository:
  rL LLVM

https://reviews.llvm.org/D43267