[PATCH] D42580: [ARM] Armv8.2-A FP16 code generation (part 2/3)

[Oliver Stannard via Phabricator via llvm-commits]

olista01 added a comment.

I'm still not convinced about the correctness of this transformation: you are turning code which contains truncates and extends into code that doesn't, without checking whether the top 16 bits could be relevant. This happens to be OK if the value is coming from/going to an fp16 arithmetic instruction, which ignores/clears the top 16 bits, but I don't think it's correct in all cases.

I think a better way to do this would be:

- Define the new DAG nodes as clearing/ignoring the top 16 bits on the i32 side, and lower it to the vmov.i16 instructions which do this.
- Lower bitcasts involving f16 to these DAG nodes, without checking what instructions are around them.
- Add DAG combines to fold zexts and truncates into the new nodes where that is legal.


https://reviews.llvm.org/D42580