[PATCH] D42580: [ARM] Armv8.2-A FP16 code generation (part 2/3)

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer updated this revision to Diff 131935.
SjoerdMeijer added a comment.

Addressed comments:

1. New ARM ISD nodes VMOVhr and VMOVrh have been introduced

to model moving half argument from int to fp registers and vice versa.
For example, for reading half arguments, the DAG looks like this:

    t2: i32,ch = CopyFromReg t0, Register:i32 %0
  t18: f16 = ARMISD::VMOVhr t2
  ...

and for writing the return value:

       ...
     t20: i32 = ARMISD::VMOVrh t11
  t16: ch,glue = CopyToReg t0, Register:i32 %r0, t20

2. Restricted the rewrite of Bitcasts further to avoid it triggering

where it shouldn't by checking the EntryNode and RET_FLAG nodes.


https://reviews.llvm.org/D42580

Files:
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/ARMISelLowering.h
  lib/Target/ARM/ARMInstrVFP.td
  test/CodeGen/ARM/fp16-instructions.ll

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