[PATCH] D42377: [CodeGen] Use MIR syntax for MachineMemOperand printing

[Francis Visoiu Mistrih via Phabricator via llvm-commits]

thegameg created this revision.
thegameg added reviewers: MatzeB, qcolombet, plotfi.
Herald added subscribers: javed.absar, nhaehnle, nemanjai.

Get rid of the "; mem:" suffix and use the one we use in MIR: ":: (load 2)".

The only issue with this is that we don't have a way to represent address spaces in MIR, so I decided to keep printing it but not parsing it in MIR.

I'll work on that next (PR35970), but I didn't want to lose any information that's being printed with this commit.


https://reviews.llvm.org/D42377

Files:
  include/llvm/CodeGen/MachineMemOperand.h
  lib/CodeGen/MIRPrinter.cpp
  lib/CodeGen/MachineBasicBlock.cpp
  lib/CodeGen/MachineInstr.cpp
  lib/CodeGen/MachineOperand.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
  test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
  test/CodeGen/AArch64/aarch64-stp-cluster.ll
  test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
  test/CodeGen/AMDGPU/extload-align.ll
  test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
  test/CodeGen/AMDGPU/syncscopes.ll
  test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll
  test/CodeGen/ARM/ldrd-memoper.ll
  test/CodeGen/ARM/misched-int-basic-thumb2.mir
  test/CodeGen/ARM/single-issue-r52.mir
  test/CodeGen/Hexagon/post-inc-aa-metadata.ll
  test/CodeGen/MIR/AMDGPU/syncscopes.mir
  test/CodeGen/PowerPC/byval-agg-info.ll
  test/CodeGen/PowerPC/combine_loads_from_build_pair.ll
  test/CodeGen/PowerPC/unal-vec-negarith.ll
  test/CodeGen/X86/GlobalISel/x86_64-fallback.ll
  test/CodeGen/X86/merge-store-partially-alias-loads.ll
  test/CodeGen/X86/stack-protector-weight.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D42377.130895.patch
Type: text/x-patch
Size: 46190 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180122/529f1ba4/attachment-0001.bin>