[PATCH] D41794: [X86] Improve AVX1 shuffle lowering for v8f32 shuffles where the low half comes from V1 and the high half comes from V2 and the halves do the same operation

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

bYeah there may be some crossover with lowerVectorShuffleByMerging128BitLanes. I'll see if I can generalize lowerVectorShuffleByMerging128BitLanes more.



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Comment at: lib/Target/X86/X86ISelLowering.cpp:10761
+  int Size = Mask.size();
+  SmallVector<int, 8> RepeatMask(Size, -1);
+
----------------
RKSimon wrote:
> Should't RepeatMask be just LaneSize wide? 
Yes it should.


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Comment at: lib/Target/X86/X86ISelLowering.cpp:10791
+    PermuteMask[i] = M;
+    if (PermuteMask[i] < 0)
+      continue;
----------------
RKSimon wrote:
> Do we gain anything by relaxing this and keeping PermuteMask[i] as UNDEF if the original Mask[i] was UNDEF?
Not sure. I was trying to create a repeated lane shuffle so its based on both lanes. If its undef in both lanes it will be undef here.


Repository:
  rL LLVM

https://reviews.llvm.org/D41794