[PATCH] D41235: [DAGCOmbine] Ensure that (brcond (setcc ...)) is handled in a canonical manner.

[Nirav Dave via Phabricator via llvm-commits]

niravd added inline comments.


================
Comment at: test/CodeGen/X86/live-out-reg-info.ll:15
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    shrl $23, %eax
+; CHECK-NEXT:    testb $1, %ah
----------------
deadalnix wrote:
> niravd wrote:
> > It looks like all the bittest patterns are no longer being matched because of the DAG change. 
> Could you point me to the code that generate these patterns so it can be fixed ?
> 
> More generally, this match is likely broken half the time in the wild right now, because the form generated depends on the order in which nodes are processed in the DAGCombiner.
It's likely a missed case in the BT instruction generation in X86ISelLowering.cpp 

Incidentally D41293 has a somewhat related change that improves DAG node fusion in instruction selection. It doesn't resolve this issue (though it exposes a similar missing case in unfoldMemoryOperand) but using both of these patches exposes a matching issue in a Hexagon test which you may be interested in. 


https://reviews.llvm.org/D41235