[llvm] r321259 - [DAGCombine] Improve ReduceLoadWidth for SRL
Sam Parker via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 22 00:38:27 PST 2017
Hi Bill,
Thanks for letting me know, I've reverted in the patch in r321349.
Regards,
sam
Sam Parker
Compilation Tools Engineer | Arm
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Arm.com
________________________________
From: Bill Seurer <seurer at linux.vnet.ibm.com>
Sent: 22 December 2017 07:18:25
To: Sam Parker; llvm-commits at lists.llvm.org
Subject: Re: [llvm] r321259 - [DAGCombine] Improve ReduceLoadWidth for SRL
This revision is causing problems on powerpc64 BE (but not LE). On a
multistage build clang fails when running many of the tests but
especially sanitizer tests. You can see where the failures began here:
http://lab.llvm.org:8011/buildslaves/ppc64be-sanitizer
One example from a check-all:
[1/458] : && /home/seurer/llvm/install/llvm-test/bin/clang++ -fPIC
-fvisibility-inlines-hidden -Werror=date-time
-Werror=unguarded-availability-new -std=c++11 -Wall -W
-Wno-unused-parameter -Wwrite-strings -Wcast-qual
-Wmissing-field-initializers -pedantic -Wno-long-long
-Wcovered-switch-default -Wnon-virtual-dtor -Wdelete-non-virtual-dtor
-Wstring-conversion -fcolor-diagnostics -ffunction-sections
-fdata-sections -fno-common -Woverloaded-virtual -Wno-nested-anon-types
-O3 -L/home/seurer/gcc/install/gcc-6.3.0/lib64
-Wl,-allow-shlib-undefined -Wl,-O3 -Wl,--gc-sections
tools/clang/unittests/StaticAnalyzer/CMakeFiles/StaticAnalysisTests.dir/AnalyzerOptionsTest.cpp.o
-o tools/clang/unittests/StaticAnalyzer/StaticAnalysisTests
lib/libLLVMSupport.a lib/libLLVMSupport.a -lpthread lib/libgtest_main.a
lib/libgtest.a -lpthread lib/libclangBasic.a lib/libclangAnalysis.a
lib/libclangStaticAnalyzerCore.a -lpthread lib/libclangAnalysis.a
lib/libclangASTMatchers.a lib/libclangAST.a lib/libclangRewrite.a
lib/libclangLex.a lib/libclangBasic.a lib/libLLVMCore.a
lib/libLLVMBinaryFormat.a lib/libLLVMMC.a lib/libLLVMSupport.a -lz -lrt
-ldl -ltinfo -lpthread -lm lib/libLLVMDemangle.a && :
[2/458] cd
/home/seurer/llvm/build/llvm-multistage/projects/compiler-rt/lib/tsan/tests/unit
&& /home/seurer/llvm/build/llvm-multistage/./bin/clang -fPIC
-fvisibility-inlines-hidden -Werror=date-time
-Werror=unguarded-availability-new -std=c++11 -Wall -W
-Wno-unused-parameter -Wwrite-strings -Wcast-qual
-Wmissing-field-initializers -pedantic -Wno-long-long
-Wcovered-switch-default -Wnon-virtual-dtor -Wdelete-non-virtual-dtor
-Wstring-conversion -fcolor-diagnostics -ffunction-sections
-fdata-sections -Wall -std=c++11 -Wno-unused-parameter
-Wno-unknown-warning-option -fPIC -fno-builtin -fno-exceptions
-fomit-frame-pointer -funwind-tables -fno-stack-protector
-fno-sanitize=safe-stack -fvisibility=hidden -fno-lto -O3
-gline-tables-only -Wno-gnu -Wno-variadic-macros -Wno-c99-extensions
-Wno-non-virtual-dtor -fPIE -fno-rtti -Wno-covered-switch-default
-DGTEST_NO_LLVM_RAW_OSTREAM=1 -DGTEST_HAS_RTTI=0
-I/home/seurer/llvm/llvm-multistage/utils/unittest/googletest/include
-I/home/seurer/llvm/llvm-multistage/utils/unittest/googletest
-I/home/seurer/llvm/llvm-multistage/projects/compiler-rt/include
-I/home/seurer/llvm/llvm-multistage/projects/compiler-rt/lib
-I/home/seurer/llvm/llvm-multistage/projects/compiler-rt/lib/tsan/rtl
-DGTEST_HAS_RTTI=0 -m64 -c -o
TsanUnitTestsObjects.tsan_unit_test_main.cc.powerpc64.o
/home/seurer/llvm/llvm-multistage/projects/compiler-rt/lib/tsan/tests/unit/tsan_unit_test_main.cc
FAILED:
projects/compiler-rt/lib/tsan/tests/unit/TsanUnitTestsObjects.tsan_unit_test_main.cc.powerpc64.o
cd
/home/seurer/llvm/build/llvm-multistage/projects/compiler-rt/lib/tsan/tests/unit
&& /home/seurer/llvm/build/llvm-multistage/./bin/clang -fPIC
-fvisibility-inlines-hidden -Werror=date-time
-Werror=unguarded-availability-new -std=c++11 -Wall -W
-Wno-unused-parameter -Wwrite-strings -Wcast-qual
-Wmissing-field-initializers -pedantic -Wno-long-long
-Wcovered-switch-default -Wnon-virtual-dtor -Wdelete-non-virtual-dtor
-Wstring-conversion -fcolor-diagnostics -ffunction-sections
-fdata-sections -Wall -std=c++11 -Wno-unused-parameter
-Wno-unknown-warning-option -fPIC -fno-builtin -fno-exceptions
-fomit-frame-pointer -funwind-tables -fno-stack-protector
-fno-sanitize=safe-stack -fvisibility=hidden -fno-lto -O3
-gline-tables-only -Wno-gnu -Wno-variadic-macros -Wno-c99-extensions
-Wno-non-virtual-dtor -fPIE -fno-rtti -Wno-covered-switch-default
-DGTEST_NO_LLVM_RAW_OSTREAM=1 -DGTEST_HAS_RTTI=0
-I/home/seurer/llvm/llvm-multistage/utils/unittest/googletest/include
-I/home/seurer/llvm/llvm-multistage/utils/unittest/googletest
-I/home/seurer/llvm/llvm-multistage/projects/compiler-rt/include
-I/home/seurer/llvm/llvm-multistage/projects/compiler-rt/lib
-I/home/seurer/llvm/llvm-multistage/projects/compiler-rt/lib/tsan/rtl
-DGTEST_HAS_RTTI=0 -m64 -c -o
TsanUnitTestsObjects.tsan_unit_test_main.cc.powerpc64.o
/home/seurer/llvm/llvm-multistage/projects/compiler-rt/lib/tsan/tests/unit/tsan_unit_test_main.cc
clang-6.0:
/home/seurer/llvm/llvm-multistage/tools/clang/include/clang/Sema/AttributeList.h:425:
clang::ArgsUnion clang::AttributeList::getArg(unsigned int) const:
Assertion `Arg < NumArgs && "Arg access out of range!"' failed.
#0 0x0000000011de472c PrintStackTraceSignalHandler(void*)
(/home/seurer/llvm/build/llvm-multistage/bin/clang-6.0+0x11de472c)
#1 0x0000000011de4bc0 SignalHandler(int)
(/home/seurer/llvm/build/llvm-multistage/bin/clang-6.0+0x11de4bc0)
#2 0x00003fff89560478 0x478 __GI_abort
#3 0x00003fff89560478
#4 0x00003fff89560478 __assert_fail_base (+0x478)
#5 0x00003fff88ea35c8 __GI___assert_fail (/lib64/libc.so.6+0x635c8)
#6 0x00003fff88e96e7c
clang::Sema::checkStringLiteralArgumentAttr(clang::AttributeList const&,
unsigned int, llvm::StringRef&, clang::SourceLocation*)
(/lib64/libc.so.6+0x56e7c)
#7 0x00003fff88e96f6c ProcessDeclAttribute(clang::Sema&, clang::Scope*,
clang::Decl*, clang::AttributeList const&, bool) (/lib64/libc.so.6+0x56f6c)
#8 0x00000000131d824c
clang::Sema::ProcessDeclAttributeList(clang::Scope*, clang::Decl*,
clang::AttributeList const*, bool)
(/home/seurer/llvm/build/llvm-multistage/bin/clang-6.0+0x131d824c)
#9 0x00000000131ed8f4 clang::Sema::ActOnStartNamespaceDef(clang::Scope*,
clang::SourceLocation, clang::SourceLocation, clang::SourceLocation,
clang::IdentifierInfo*, clang::SourceLocation, clang::AttributeList*,
clang::UsingDirectiveDecl*&)
(/home/seurer/llvm/build/llvm-multistage/bin/clang-6.0+0x131ed8f4)
#10 0x00000000131e5398 clang::Parser::ParseNamespace(unsigned int,
clang::SourceLocation&, clang::SourceLocation)
(/home/seurer/llvm/build/llvm-multistage/bin/clang-6.0+0x131e5398)
#11 0x000000001329783c clang::Parser::ParseDeclaration(unsigned int,
clang::SourceLocation&, clang::Parser::ParsedAttributesWithRange&)
(/home/seurer/llvm/build/llvm-multistage/bin/clang-6.0+0x1329783c)
#12 0x0000000012e23abc
clang::Parser::ParseExternalDeclaration(clang::Parser::ParsedAttributesWithRange&,
clang::ParsingDeclSpec*)
(/home/seurer/llvm/build/llvm-multistage/bin/clang-6.0+0x12e23abc)
#13 0x0000000012e0cd84
clang::Parser::ParseInnerNamespace(std::vector<clang::SourceLocation,
std::allocator<clang::SourceLocation> >&,
std::vector<clang::IdentifierInfo*,
std::allocator<clang::IdentifierInfo*> >&,
std::vector<clang::SourceLocation, std::allocator<clang::SourceLocation>
>&, unsigned int, clang::SourceLocation&, clang::ParsedAttributes&,
clang::BalancedDelimiterTracker&)
(/home/seurer/llvm/build/llvm-multistage/bin/clang-6.0+0x12e0cd84)
#14 0x0000000012df22c8 clang::Parser::ParseNamespace(unsigned int,
clang::SourceLocation&, clang::SourceLocation)
(/home/seurer/llvm/build/llvm-multistage/bin/clang-6.0+0x12df22c8)
#15 0x0000000012e241a8 clang::Parser::ParseDeclaration(unsigned int,
clang::SourceLocation&, clang::Parser::ParsedAttributesWithRange&)
(/home/seurer/llvm/build/llvm-multistage/bin/clang-6.0+0x12e241a8)
#16 0x0000000012e23b20
clang::Parser::ParseExternalDeclaration(clang::Parser::ParsedAttributesWithRange&,
clang::ParsingDeclSpec*)
(/home/seurer/llvm/build/llvm-multistage/bin/clang-6.0+0x12e23b20)
#17 0x0000000012e0cb64
clang::Parser::ParseTopLevelDecl(clang::OpaquePtr<clang::DeclGroupRef>&)
(/home/seurer/llvm/build/llvm-multistage/bin/clang-6.0+0x12e0cb64)
#18 0x0000000012df22c8 clang::ParseAST(clang::Sema&, bool, bool)
(/home/seurer/llvm/build/llvm-multistage/bin/clang-6.0+0x12df22c8)
#19 0x0000000012df1b6c clang::ASTFrontendAction::ExecuteAction()
(/home/seurer/llvm/build/llvm-multistage/bin/clang-6.0+0x12df1b6c)
#20 0x0000000012decb58 clang::CodeGenAction::ExecuteAction()
(/home/seurer/llvm/build/llvm-multistage/bin/clang-6.0+0x12decb58)
#21 0x0000000012444830 clang::FrontendAction::Execute()
(/home/seurer/llvm/build/llvm-multistage/bin/clang-6.0+0x12444830)
#22 0x000000001282bcb0
clang::CompilerInstance::ExecuteAction(clang::FrontendAction&)
(/home/seurer/llvm/build/llvm-multistage/bin/clang-6.0+0x1282bcb0)
#23 0x0000000012443e70
clang::ExecuteCompilerInvocation(clang::CompilerInstance*)
(/home/seurer/llvm/build/llvm-multistage/bin/clang-6.0+0x12443e70)
#24 0x00000000123fa200 cc1_main(llvm::ArrayRef<char const*>, char
const*, void*)
(/home/seurer/llvm/build/llvm-multistage/bin/clang-6.0+0x123fa200)
#25 0x00000000124fd060 main
(/home/seurer/llvm/build/llvm-multistage/bin/clang-6.0+0x124fd060)
#26 0x000000001046cfec generic_start_main.isra.0
(/home/seurer/llvm/build/llvm-multistage/bin/clang-6.0+0x1046cfec)
#27 0x000000001046ab48 __libc_start_main
(/home/seurer/llvm/build/llvm-multistage/bin/clang-6.0+0x1046ab48)
On 12/21/2017 06:55 AM, Sam Parker via llvm-commits wrote:
> Author: sam_parker
> Date: Thu Dec 21 04:55:04 2017
> New Revision: 321259
>
> URL: http://llvm.org/viewvc/llvm-project?rev=321259&view=rev
> Log:
> [DAGCombine] Improve ReduceLoadWidth for SRL
>
> If the SRL node is only used by an AND, we may be able to set the
> ExtVT to the width of the mask, making the AND redundant. To support
> this, another check has been added in isLegalNarrowLoad which queries
> whether the load is valid.
>
> Differential Revision: https://reviews.llvm.org/D41350
>
> Modified:
> llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> llvm/trunk/test/CodeGen/ARM/shift-combine.ll
> llvm/trunk/test/CodeGen/X86/h-registers-1.ll
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=321259&r1=321258&r2=321259&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Dec 21 04:55:04 2017
> @@ -3788,6 +3788,16 @@ bool DAGCombiner::isLegalNarrowLoad(Load
> if (LoadN->getNumValues() > 2)
> return false;
>
> + // Only allow byte offsets.
> + if (ShAmt % 8)
> + return false;
> +
> + // Ensure that this isn't going to produce an unsupported unaligned access.
> + if (ShAmt && !TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
> + ExtVT, LoadN->getAddressSpace(),
> + ShAmt / 8))
> + return false;
> +
> // If the load that we're shrinking is an extload and we're not just
> // discarding the extension we can't simply shrink the load. Bail.
> // TODO: It would be possible to merge the extensions in some cases.
> @@ -8274,6 +8284,22 @@ SDValue DAGCombiner::ReduceLoadWidth(SDN
> // then the result of the shift+trunc is zero/undef (handled elsewhere).
> if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
> return SDValue();
> +
> + // If the SRL is only used by a masking AND, we may be able to adjust
> + // the ExtVT to make the AND redundant.
> + SDNode *Mask = *(N->use_begin());
> + if (Mask->getOpcode() == ISD::AND &&
> + isa<ConstantSDNode>(Mask->getOperand(1))) {
> + const APInt &ShiftMask =
> + cast<ConstantSDNode>(Mask->getOperand(1))->getAPIntValue();
> + if (ShiftMask.isMask()) {
> + EVT MaskedVT = EVT::getIntegerVT(*DAG.getContext(),
> + ShiftMask.countTrailingOnes());
> + // Recompute the type.
> + if (TLI.isLoadExtLegal(ExtType, N0.getValueType(), MaskedVT))
> + ExtVT = MaskedVT;
> + }
> + }
> }
> }
>
>
> Modified: llvm/trunk/test/CodeGen/ARM/shift-combine.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/shift-combine.ll?rev=321259&r1=321258&r2=321259&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/shift-combine.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/shift-combine.ll Thu Dec 21 04:55:04 2017
> @@ -217,10 +217,23 @@ entry:
> ret i32 %conv
> }
>
> -; CHECK-LABEL: test_shift8_mask8
> +; CHECK-LABEL: test_shift7_mask8
> ; CHECK-BE: ldr r1, [r0]
> ; CHECK-COMMON: ldr r1, [r0]
> -; CHECK-COMMON: ubfx r1, r1, #8, #8
> +; CHECK-COMMON: ubfx r1, r1, #7, #8
> +; CHECK-COMMON: str r1, [r0]
> +define arm_aapcscc void @test_shift7_mask8(i32* nocapture %p) {
> +entry:
> + %0 = load i32, i32* %p, align 4
> + %shl = lshr i32 %0, 7
> + %and = and i32 %shl, 255
> + store i32 %and, i32* %p, align 4
> + ret void
> +}
> +
> +; CHECK-LABEL: test_shift8_mask8
> +; CHECK-BE: ldrb r1, [r0, #2]
> +; CHECK-COMMON: ldrb r1, [r0, #1]
> ; CHECK-COMMON: str r1, [r0]
> define arm_aapcscc void @test_shift8_mask8(i32* nocapture %p) {
> entry:
> @@ -231,10 +244,40 @@ entry:
> ret void
> }
>
> -; CHECK-LABEL: test_shift8_mask16
> +; CHECK-LABEL: test_shift8_mask7
> +; CHECK-BE: ldr r1, [r0]
> +; CHECK-COMMON: ldr r1, [r0]
> +; CHECK-COMMON: ubfx r1, r1, #8, #7
> +; CHECK-COMMON: str r1, [r0]
> +define arm_aapcscc void @test_shift8_mask7(i32* nocapture %p) {
> +entry:
> + %0 = load i32, i32* %p, align 4
> + %shl = lshr i32 %0, 8
> + %and = and i32 %shl, 127
> + store i32 %and, i32* %p, align 4
> + ret void
> +}
> +
> +; CHECK-LABEL: test_shift9_mask8
> ; CHECK-BE: ldr r1, [r0]
> ; CHECK-COMMON: ldr r1, [r0]
> -; CHECK-COMMON: ubfx r1, r1, #8, #16
> +; CHECK-COMMON: ubfx r1, r1, #9, #8
> +; CHECK-COMMON: str r1, [r0]
> +define arm_aapcscc void @test_shift9_mask8(i32* nocapture %p) {
> +entry:
> + %0 = load i32, i32* %p, align 4
> + %shl = lshr i32 %0, 9
> + %and = and i32 %shl, 255
> + store i32 %and, i32* %p, align 4
> + ret void
> +}
> +
> +; CHECK-LABEL: test_shift8_mask16
> +; CHECK-ALIGN: ldr r1, [r0]
> +; CHECK-ALIGN: ubfx r1, r1, #8, #16
> +; CHECK-BE: ldrh r1, [r0, #1]
> +; CHECK-ARM: ldrh r1, [r0, #1]
> +; CHECK-THUMB: ldrh.w r1, [r0, #1]
> ; CHECK-COMMON: str r1, [r0]
> define arm_aapcscc void @test_shift8_mask16(i32* nocapture %p) {
> entry:
> @@ -243,6 +286,61 @@ entry:
> %and = and i32 %shl, 65535
> store i32 %and, i32* %p, align 4
> ret void
> +}
> +
> +; CHECK-LABEL: test_shift15_mask16
> +; CHECK-COMMON: ldr r1, [r0]
> +; CHECK-COMMON: ubfx r1, r1, #15, #16
> +; CHECK-COMMON: str r1, [r0]
> +define arm_aapcscc void @test_shift15_mask16(i32* nocapture %p) {
> +entry:
> + %0 = load i32, i32* %p, align 4
> + %shl = lshr i32 %0, 15
> + %and = and i32 %shl, 65535
> + store i32 %and, i32* %p, align 4
> + ret void
> +}
> +
> +; CHECK-LABEL: test_shift16_mask15
> +; CHECK-BE: ldrh r1, [r0]
> +; CHECK-COMMON: ldrh r1, [r0, #2]
> +; CHECK-COMMON: bfc r1, #15, #17
> +; CHECK-COMMON: str r1, [r0]
> +define arm_aapcscc void @test_shift16_mask15(i32* nocapture %p) {
> +entry:
> + %0 = load i32, i32* %p, align 4
> + %shl = lshr i32 %0, 16
> + %and = and i32 %shl, 32767
> + store i32 %and, i32* %p, align 4
> + ret void
> +}
> +
> +; CHECK-LABEL: test_shift8_mask24
> +; CHECK-BE: ldr r1, [r0]
> +; CHECK-COMMON: ldr r1, [r0]
> +; CHECK-ARM: lsr r1, r1, #8
> +; CHECK-THUMB: lsrs r1, r1, #8
> +; CHECK-COMMON: str r1, [r0]
> +define arm_aapcscc void @test_shift8_mask24(i32* nocapture %p) {
> +entry:
> + %0 = load i32, i32* %p, align 4
> + %shl = lshr i32 %0, 8
> + %and = and i32 %shl, 16777215
> + store i32 %and, i32* %p, align 4
> + ret void
> +}
> +
> +; CHECK-LABEL: test_shift24_mask16
> +; CHECK-BE: ldrb r1, [r0]
> +; CHECK-COMMON: ldrb r1, [r0, #3]
> +; CHECK-COMMON: str r1, [r0]
> +define arm_aapcscc void @test_shift24_mask16(i32* nocapture %p) {
> +entry:
> + %0 = load i32, i32* %p, align 4
> + %shl = lshr i32 %0, 24
> + %and = and i32 %shl, 65535
> + store i32 %and, i32* %p, align 4
> + ret void
> }
>
> ; CHECK-LABEL: test_sext_shift8_mask8
>
> Modified: llvm/trunk/test/CodeGen/X86/h-registers-1.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/h-registers-1.ll?rev=321259&r1=321258&r2=321259&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/h-registers-1.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/h-registers-1.ll Thu Dec 21 04:55:04 2017
> @@ -22,21 +22,18 @@ define i64 @foo(i64 %a, i64 %b, i64 %c,
> ; CHECK-NEXT: movzbl %ah, %eax # NOREX
> ; CHECK-NEXT: movq %rax, %r10
> ; CHECK-NEXT: movzbl %dh, %edx # NOREX
> -; CHECK-NEXT: movzbl %ch, %eax # NOREX
> -; CHECK-NEXT: movq %rax, %r11
> +; CHECK-NEXT: movzbl %ch, %ebp # NOREX
> ; CHECK-NEXT: movq %r8, %rax
> ; CHECK-NEXT: movzbl %ah, %ecx # NOREX
> ; CHECK-NEXT: movq %r9, %rax
> -; CHECK-NEXT: movzbl %ah, %ebp # NOREX
> -; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
> -; CHECK-NEXT: movzbl %ah, %eax # NOREX
> -; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %ebx
> -; CHECK-NEXT: movzbl %bh, %edi # NOREX
> +; CHECK-NEXT: movzbl %ah, %ebx # NOREX
> +; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
> +; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %edi
> ; CHECK-NEXT: movq %r10, %r8
> ; CHECK-NEXT: addq %r8, %rsi
> -; CHECK-NEXT: addq %r11, %rdx
> +; CHECK-NEXT: addq %rbp, %rdx
> ; CHECK-NEXT: addq %rsi, %rdx
> -; CHECK-NEXT: addq %rbp, %rcx
> +; CHECK-NEXT: addq %rbx, %rcx
> ; CHECK-NEXT: addq %rdi, %rax
> ; CHECK-NEXT: addq %rcx, %rax
> ; CHECK-NEXT: addq %rdx, %rax
> @@ -58,21 +55,18 @@ define i64 @foo(i64 %a, i64 %b, i64 %c,
> ; GNUX32-NEXT: movzbl %ah, %eax # NOREX
> ; GNUX32-NEXT: movq %rax, %r10
> ; GNUX32-NEXT: movzbl %dh, %edx # NOREX
> -; GNUX32-NEXT: movzbl %ch, %eax # NOREX
> -; GNUX32-NEXT: movq %rax, %r11
> +; GNUX32-NEXT: movzbl %ch, %ebp # NOREX
> ; GNUX32-NEXT: movq %r8, %rax
> ; GNUX32-NEXT: movzbl %ah, %ecx # NOREX
> ; GNUX32-NEXT: movq %r9, %rax
> -; GNUX32-NEXT: movzbl %ah, %ebp # NOREX
> -; GNUX32-NEXT: movl {{[0-9]+}}(%esp), %eax
> -; GNUX32-NEXT: movzbl %ah, %eax # NOREX
> -; GNUX32-NEXT: movl {{[0-9]+}}(%esp), %ebx
> -; GNUX32-NEXT: movzbl %bh, %edi # NOREX
> +; GNUX32-NEXT: movzbl %ah, %ebx # NOREX
> +; GNUX32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
> +; GNUX32-NEXT: movzbl {{[0-9]+}}(%esp), %edi
> ; GNUX32-NEXT: movq %r10, %r8
> ; GNUX32-NEXT: addq %r8, %rsi
> -; GNUX32-NEXT: addq %r11, %rdx
> +; GNUX32-NEXT: addq %rbp, %rdx
> ; GNUX32-NEXT: addq %rsi, %rdx
> -; GNUX32-NEXT: addq %rbp, %rcx
> +; GNUX32-NEXT: addq %rbx, %rcx
> ; GNUX32-NEXT: addq %rdi, %rax
> ; GNUX32-NEXT: addq %rcx, %rax
> ; GNUX32-NEXT: addq %rdx, %rax
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits
>
--
-Bill Seurer
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