[PATCH] D41040: [DAGCombiner] protect against an infinite loop between shl <--> mul (PR35579)

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:2678
+      DAG.isKnownToBeAPowerOfTwo(N1) &&
+      (!VT.isVector() || Level <= AfterLegalizeVectorOps)) {
     SDLoc DL(N);
----------------
RKSimon wrote:
> This looks OK, but would !LegalOperations || TLI.isOperationLegal(ISD::SHL, VT) be better?
That would be safer, but 'make check' shows we'll lose a fold for cases like this:


```
; fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
define <4 x i32> @combine_vec_urem_by_shl_pow2a(<4 x i32> %x, <4 x i32> %y) {
  %1 = shl <4 x i32> <i32 4, i32 4, i32 4, i32 4>, %y
  %2 = urem <4 x i32> %x, %1
  ret <4 x i32> %2
}

```
-; SSE-NEXT:    pslld $2, %xmm1
+; SSE-NEXT:    pmulld {{.*}}(%rip), %xmm1

We can't ask 'isOperationLegalOrCustom()' because then we'd still hit the infinite loop.


https://reviews.llvm.org/D41040