[PATCH] D41040: [DAGCombiner] protect against an infinite loop between shl <--> mul (PR35579)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a reviewer: RKSimon.
RKSimon added inline comments.


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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:2678
+      DAG.isKnownToBeAPowerOfTwo(N1) &&
+      (!VT.isVector() || Level <= AfterLegalizeVectorOps)) {
     SDLoc DL(N);
----------------
This looks OK, but would !LegalOperations || TLI.isOperationLegal(ISD::SHL, VT) be better?


https://reviews.llvm.org/D41040