[llvm] r318710 - Revert r318678 to fix Clang test
Richard Trieu via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 20 16:12:18 PST 2017
Author: rtrieu
Date: Mon Nov 20 16:12:18 2017
New Revision: 318710
URL: http://llvm.org/viewvc/llvm-project?rev=318710&view=rev
Log:
Revert r318678 to fix Clang test
r318678 caused the Clang test CodeGen/ms-inline-asm.c to start failing.
Modified:
llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
llvm/trunk/lib/Target/X86/X86InstrFormats.td
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/lib/Target/X86/X86InstrSystem.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/test/MC/Disassembler/X86/x86-16.txt
llvm/trunk/test/MC/X86/x86-16.s
llvm/trunk/test/MC/X86/x86-32.s
llvm/trunk/test/MC/X86/x86-64.s
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h?rev=318710&r1=318709&r2=318710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h Mon Nov 20 16:12:18 2017
@@ -366,15 +366,13 @@ namespace X86II {
// OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix.
// OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in
// 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66
- // prefix in 16-bit mode. OpSizeIgnore means that the instruction may
- // take a optional 0x66 byte but should not emit with one.
+ // prefix in 16-bit mode.
OpSizeShift = 7,
OpSizeMask = 0x3 << OpSizeShift,
- OpSizeFixed = 0 << OpSizeShift,
- OpSize16 = 1 << OpSizeShift,
- OpSize32 = 2 << OpSizeShift,
- OpSizeIgnore = 3 << OpSizeShift,
+ OpSizeFixed = 0 << OpSizeShift,
+ OpSize16 = 1 << OpSizeShift,
+ OpSize32 = 2 << OpSizeShift,
// AsSize - AdSizeX implies this instruction determines its need of 0x67
// prefix from a normal ModRM memory operand. The other types indicate that
Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=318710&r1=318709&r2=318710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Mon Nov 20 16:12:18 2017
@@ -157,10 +157,9 @@ def EncEVEX : Encoding<3>;
class OperandSize<bits<2> val> {
bits<2> Value = val;
}
-def OpSizeFixed : OperandSize<0>; // Never needs a 0x66 prefix.
-def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
-def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
-def OpSizeIgnore : OperandSize<3>; // Takes 0x66 prefix, never emits.
+def OpSizeFixed : OperandSize<0>; // Never needs a 0x66 prefix.
+def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
+def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
// Address size for encodings that change based on mode.
class AddressSize<bits<2> val> {
@@ -175,7 +174,6 @@ def AdSize64 : AddressSize<3>; // Encode
// emitter that various prefix bytes are required.
class OpSize16 { OperandSize OpSize = OpSize16; }
class OpSize32 { OperandSize OpSize = OpSize32; }
-class OpSizeIgnore { OperandSize OpSize = OpSizeIgnore; }
class AdSize16 { AddressSize AdSize = AdSize16; }
class AdSize32 { AddressSize AdSize = AdSize32; }
class AdSize64 { AddressSize AdSize = AdSize64; }
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=318710&r1=318709&r2=318710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Nov 20 16:12:18 2017
@@ -3157,8 +3157,8 @@ def : InstAlias<"jmpl\t$seg, $off", (FA
// Force mov without a suffix with a segment and mem to prefer the 'l' form of
// the move. All segment/mem forms are equivalent, this has the shortest
// encoding.
-def : InstAlias<"mov\t{$mem, $seg|$seg, $mem}", (MOV16sm SEGMENT_REG:$seg, i16mem:$mem), 0>;
-def : InstAlias<"mov\t{$seg, $mem|$mem, $seg}", (MOV16ms i16mem:$mem, SEGMENT_REG:$seg), 0>;
+def : InstAlias<"mov\t{$mem, $seg|$seg, $mem}", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem), 0>;
+def : InstAlias<"mov\t{$seg, $mem|$mem, $seg}", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg), 0>;
// Match 'movq <largeimm>, <reg>' as an alias for movabsq.
def : InstAlias<"mov{q}\t{$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>;
Modified: llvm/trunk/lib/Target/X86/X86InstrSystem.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSystem.td?rev=318710&r1=318709&r2=318710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSystem.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSystem.td Mon Nov 20 16:12:18 2017
@@ -175,7 +175,11 @@ def MOV64rs : RI<0x8C, MRMDestReg, (outs
"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
let mayStore = 1 in {
def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src),
- "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSizeIgnore;
+ "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize16;
+def MOV32ms : I<0x8C, MRMDestMem, (outs), (ins i32mem:$dst, SEGMENT_REG:$src),
+ "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize32;
+def MOV64ms : RI<0x8C, MRMDestMem, (outs), (ins i64mem:$dst, SEGMENT_REG:$src),
+ "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;
}
def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize16;
@@ -185,7 +189,11 @@ def MOV64sr : RI<0x8E, MRMSrcReg, (outs
"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
let mayLoad = 1 in {
def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
- "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSizeIgnore;
+ "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize16;
+def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
+ "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize32;
+def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
+ "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;
}
} // SchedRW
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=318710&r1=318709&r2=318710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Mon Nov 20 16:12:18 2017
@@ -1550,7 +1550,7 @@ def SBWriteResGroup49 : SchedWriteRes<[S
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup49], (instregex "JMP(16|32|64)m")>;
-def: InstRW<[SBWriteResGroup49], (instregex "MOV16sm")>;
+def: InstRW<[SBWriteResGroup49], (instregex "MOV64sm")>;
def SBWriteResGroup50 : SchedWriteRes<[SBPort23,SBPort05]> {
let Latency = 6;
Modified: llvm/trunk/test/MC/Disassembler/X86/x86-16.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-16.txt?rev=318710&r1=318709&r2=318710&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/x86-16.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/x86-16.txt Mon Nov 20 16:12:18 2017
@@ -207,7 +207,7 @@
# CHECK: movw %cs, %ax
0x8c 0xc8
-# CHECK: movw %cs, (%eax)
+# CHECK: movl %cs, (%eax)
0x67 0x66 0x8c 0x08
# CHECK: movw %cs, (%eax)
@@ -216,7 +216,7 @@
# CHECK: movl %eax, %cs
0x66 0x8e 0xc8
-# CHECK: movw (%eax), %cs
+# CHECK: movl (%eax), %cs
0x67 0x66 0x8e 0x08
# CHECK: movw (%eax), %cs
Modified: llvm/trunk/test/MC/X86/x86-16.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-16.s?rev=318710&r1=318709&r2=318710&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-16.s (original)
+++ llvm/trunk/test/MC/X86/x86-16.s Mon Nov 20 16:12:18 2017
@@ -248,9 +248,9 @@ cmovnae %bx,%bx
// CHECK: encoding: [0x8c,0xc8]
movw %cs, %ax
-// CHECK: movw %cs, (%eax)
-// CHECK: encoding: [0x67,0x8c,0x08]
- mov %cs, (%eax)
+// CHECK: movl %cs, (%eax)
+// CHECK: encoding: [0x67,0x66,0x8c,0x08]
+ movl %cs, (%eax)
// CHECK: movw %cs, (%eax)
// CHECK: encoding: [0x67,0x8c,0x08]
@@ -272,9 +272,9 @@ cmovnae %bx,%bx
// CHECK: encoding: [0x8e,0xc8]
mov %ax, %cs
-// CHECK: movw (%eax), %cs
-// CHECK: encoding: [0x67,0x8e,0x08]
- mov (%eax), %cs
+// CHECK: movl (%eax), %cs
+// CHECK: encoding: [0x67,0x66,0x8e,0x08]
+ movl (%eax), %cs
// CHECK: movw (%eax), %cs
// CHECK: encoding: [0x67,0x8e,0x08]
Modified: llvm/trunk/test/MC/X86/x86-32.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32.s?rev=318710&r1=318709&r2=318710&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-32.s (original)
+++ llvm/trunk/test/MC/X86/x86-32.s Mon Nov 20 16:12:18 2017
@@ -355,12 +355,12 @@ cmovnae %bx,%bx
// CHECK: encoding: [0x66,0x8c,0xc8]
movw %cs, %ax
-// CHECK: movw %cs, (%eax)
+// CHECK: movl %cs, (%eax)
// CHECK: encoding: [0x8c,0x08]
- mov %cs, (%eax)
+ movl %cs, (%eax)
// CHECK: movw %cs, (%eax)
-// CHECK: encoding: [0x8c,0x08]
+// CHECK: encoding: [0x66,0x8c,0x08]
movw %cs, (%eax)
// CHECK: movl %eax, %cs
@@ -379,12 +379,12 @@ cmovnae %bx,%bx
// CHECK: encoding: [0x8e,0xc8]
mov %ax, %cs
-// CHECK: movw (%eax), %cs
+// CHECK: movl (%eax), %cs
// CHECK: encoding: [0x8e,0x08]
- mov (%eax), %cs
+ movl (%eax), %cs
// CHECK: movw (%eax), %cs
-// CHECK: encoding: [0x8e,0x08]
+// CHECK: encoding: [0x66,0x8e,0x08]
movw (%eax), %cs
// radr://8033374
Modified: llvm/trunk/test/MC/X86/x86-64.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=318710&r1=318709&r2=318710&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-64.s (original)
+++ llvm/trunk/test/MC/X86/x86-64.s Mon Nov 20 16:12:18 2017
@@ -1082,8 +1082,8 @@ decl %eax // CHECK: decl %eax # encoding
// rdar://8208615
-mov (%rsi), %gs // CHECK: movw (%rsi), %gs # encoding: [0x8e,0x2e]
-mov %gs, (%rsi) // CHECK: movw %gs, (%rsi) # encoding: [0x8c,0x2e]
+mov (%rsi), %gs // CHECK: movl (%rsi), %gs # encoding: [0x8e,0x2e]
+mov %gs, (%rsi) // CHECK: movl %gs, (%rsi) # encoding: [0x8c,0x2e]
// rdar://8431864
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