[PATCH] D40061: [WIP] [ARM] Make MachineVerifier more strict about terminators

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

> So now you make all returns (predicated or not) non-analyzable from analyzeBranch's perspective?

Yes.

> but have you looked at the different analyzeBranch implementations?

I just tried looking.  I think this is consistent with what other targets do (e.g. PowerPC has a conditional return instruction, which it treats an unanalyzable).


Repository:
  rL LLVM

https://reviews.llvm.org/D40061