[PATCH] D40155: AMDGPU: Fix breaking SMEM clauses

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: lib/Target/AMDGPU/GCNHazardRecognizer.cpp:280
+void GCNHazardRecognizer::addClauseInst(const MachineInstr &MI) {
+  // XXX: Do we need to worry about implicit operands
+  addRegsToSet(TRI, MI.defs(), ClauseDefs);
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t-tye wrote:
> Can implicit operands be registers? Is the only such case M0 which can never be modified. So probably not?
Implicit operands are only registers. In this case it could only be operands that aren't actually read or written by the instruction, but something added them for modeling some other constraint.


https://reviews.llvm.org/D40155