[PATCH] D35192: [ARM] Use ADDCARRY / SUBCARRY

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added a comment.

Hmm, scheduling is correct. I was all wrong, the legalized DAG is already wrong.

  typedef unsigned int mp_digit;
  typedef unsigned long long mp_word;
  
  int
  foo(mp_digit vreg0, mp_digit vreg1, mp_digit vreg2, mp_digit vreg3, mp_digit vreg4)
  {
      mp_digit carry = 0;
  
      mp_word w1 = ((mp_word)0) + (vreg2) + (vreg0);
      mp_digit vreg2_2 = (mp_digit)(w1);
      mp_digit carry2 = (mp_digit)((w1) >> (8 * sizeof(mp_digit)));
  
      // int r8_1 = carry2;
  
      mp_word w2 = ((mp_word)0) + (vreg2_2) + (vreg0);
      mp_digit carry4 = (mp_digit)((w2) >> (8 * sizeof(mp_digit)));
  
      // int r8_2 = rb8_1 + carry4;
      int r8_2 = carry2 + carry4;
  
      mp_word w3 = ((mp_word)0) + (vreg3) + (vreg1);
      mp_digit carry6 = (mp_digit)((w3) >> (8 * sizeof(mp_digit)));
  
      mp_word w4 = ((mp_word)carry6) + (vreg4) + (0);
      mp_digit carry7 = (mp_digit)((w4) >> (8 * sizeof(mp_digit)));
  
      int r8_3 = r8_2 + carry7;
  
      return r8_3;
  }

Two steps of the combiner F5483198: Screenshot from 2017-11-15 17:57:07.png <https://reviews.llvm.org/F5483198>. I believe node `t57` in the right is wrong.


Repository:
  rL LLVM

https://reviews.llvm.org/D35192