[polly] r316870 - Fix two testcases. NFC intended.

Sun Oct 29 14:00:48 PDT 2017

Author: pfaffe
Date: Sun Oct 29 14:00:48 2017
New Revision: 316870

URL: http://llvm.org/viewvc/llvm-project?rev=316870&view=rev
Log:
Fix two testcases. NFC intended.

Add missing %loadPolly directive to support out of tree builds. One of
the changes is somewhat bigger, because the directive turns on LLVM
names, and the testcase deosn't use those.

Modified:
    polly/trunk/test/GPGPU/align-params-in-schedule.ll
    polly/trunk/test/GPGPU/spir-codegen.ll

Modified: polly/trunk/test/GPGPU/align-params-in-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/GPGPU/align-params-in-schedule.ll?rev=316870&r1=316869&r2=316870&view=diff
==============================================================================

--- polly/trunk/test/GPGPU/align-params-in-schedule.ll (original)
+++ polly/trunk/test/GPGPU/align-params-in-schedule.ll Sun Oct 29 14:00:48 2017
@@ -1,4 +1,4 @@
-; RUN: opt -S -polly-process-unprofitable -polly-codegen-ppcg \
+; RUN: opt %loadPolly -S -polly-process-unprofitable -polly-codegen-ppcg \
 ; RUN: -polly-invariant-load-hoisting -polly-ignore-parameter-bounds < %s | \
 ; RUN: FileCheck %s
 

Modified: polly/trunk/test/GPGPU/spir-codegen.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/GPGPU/spir-codegen.ll?rev=316870&r1=316869&r2=316870&view=diff
==============================================================================
--- polly/trunk/test/GPGPU/spir-codegen.ll (original)
+++ polly/trunk/test/GPGPU/spir-codegen.ll Sun Oct 29 14:00:48 2017
@@ -1,4 +1,4 @@
-; RUN: opt -O3 -polly -polly-target=gpu \
+; RUN: opt %loadPolly -O3 -polly -polly-target=gpu \
 ; RUN: -polly-gpu-arch=spir32 \
 ; RUN: -polly-acc-dump-kernel-ir -polly-process-unprofitable -disable-output < %s | \
 ; RUN: FileCheck %s
@@ -8,7 +8,7 @@
 ; CHECK:      target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-i128:128:128-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024"
 ; CHECK-NEXT: target triple = "spir-unknown-unknown"
 
-; CHECK-LABEL: define spir_kernel void @FUNC_double_parallel_loop_SCOP_0_KERNEL_0(i8 addrspace(1)* %MemRef0) #0 !kernel_arg_addr_space !0 !kernel_arg_name !1 !kernel_arg_access_qual !1 !kernel_arg_type !1 !kernel_arg_type_qual !1 !kernel_arg_base_type !1 {
+; CHECK-LABEL: define spir_kernel void @FUNC_double_parallel_loop_SCOP_0_KERNEL_0(i8 addrspace(1)* %MemRef_A) #0 !kernel_arg_addr_space !0 !kernel_arg_name !1 !kernel_arg_access_qual !1 !kernel_arg_type !1 !kernel_arg_type_qual !1 !kernel_arg_base_type !1 {
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT:   %0 = call i32 @__gen_ocl_get_group_id0()
 ; CHECK-NEXT:   %__gen_ocl_get_group_id0 = zext i32 %0 to i64
@@ -36,29 +36,29 @@
 ; CHECK-LABEL: polly.stmt.bb5:                                   ; preds = %polly.loop_header
 ; CHECK-NEXT:   %10 = mul i64 %5, %9
 ; CHECK-NEXT:   %p_tmp6 = sitofp i64 %10 to float
-; CHECK-NEXT:   %polly.access.cast.MemRef0 = bitcast i8 addrspace(1)* %MemRef0 to float addrspace(1)*
+; CHECK-NEXT:   %polly.access.cast.MemRef_A = bitcast i8 addrspace(1)* %MemRef_A to float addrspace(1)*
 ; CHECK-NEXT:   %11 = mul nsw i64 32, %__gen_ocl_get_group_id0
 ; CHECK-NEXT:   %12 = add nsw i64 %11, %__gen_ocl_get_local_id0
-; CHECK-NEXT:   %polly.access.mul.MemRef0 = mul nsw i64 %12, 1024
+; CHECK-NEXT:   %polly.access.mul.MemRef_A = mul nsw i64 %12, 1024
 ; CHECK-NEXT:   %13 = mul nsw i64 32, %__gen_ocl_get_group_id1
 ; CHECK-NEXT:   %14 = add nsw i64 %13, %__gen_ocl_get_local_id1
 ; CHECK-NEXT:   %15 = mul nsw i64 16, %polly.indvar
 ; CHECK-NEXT:   %16 = add nsw i64 %14, %15
-; CHECK-NEXT:   %polly.access.add.MemRef0 = add nsw i64 %polly.access.mul.MemRef0, %16
-; CHECK-NEXT:   %polly.access.MemRef0 = getelementptr float, float addrspace(1)* %polly.access.cast.MemRef0, i64 %polly.access.add.MemRef0
-; CHECK-NEXT:   %tmp8_p_scalar_ = load float, float addrspace(1)* %polly.access.MemRef0, align 4
+; CHECK-NEXT:   %polly.access.add.MemRef_A = add nsw i64 %polly.access.mul.MemRef_A, %16
+; CHECK-NEXT:   %polly.access.MemRef_A = getelementptr float, float addrspace(1)* %polly.access.cast.MemRef_A, i64 %polly.access.add.MemRef_A
+; CHECK-NEXT:   %tmp8_p_scalar_ = load float, float addrspace(1)* %polly.access.MemRef_A, align 4
 ; CHECK-NEXT:   %p_tmp9 = fadd float %tmp8_p_scalar_, %p_tmp6
-; CHECK-NEXT:   %polly.access.cast.MemRef01 = bitcast i8 addrspace(1)* %MemRef0 to float addrspace(1)*
+; CHECK-NEXT:   %polly.access.cast.MemRef_A1 = bitcast i8 addrspace(1)* %MemRef_A to float addrspace(1)*
 ; CHECK-NEXT:   %17 = mul nsw i64 32, %__gen_ocl_get_group_id0
 ; CHECK-NEXT:   %18 = add nsw i64 %17, %__gen_ocl_get_local_id0
-; CHECK-NEXT:   %polly.access.mul.MemRef02 = mul nsw i64 %18, 1024
+; CHECK-NEXT:   %polly.access.mul.MemRef_A2 = mul nsw i64 %18, 1024
 ; CHECK-NEXT:   %19 = mul nsw i64 32, %__gen_ocl_get_group_id1
 ; CHECK-NEXT:   %20 = add nsw i64 %19, %__gen_ocl_get_local_id1
 ; CHECK-NEXT:   %21 = mul nsw i64 16, %polly.indvar
 ; CHECK-NEXT:   %22 = add nsw i64 %20, %21
-; CHECK-NEXT:   %polly.access.add.MemRef03 = add nsw i64 %polly.access.mul.MemRef02, %22
-; CHECK-NEXT:   %polly.access.MemRef04 = getelementptr float, float addrspace(1)* %polly.access.cast.MemRef01, i64 %polly.access.add.MemRef03
-; CHECK-NEXT:   store float %p_tmp9, float addrspace(1)* %polly.access.MemRef04, align 4
+; CHECK-NEXT:   %polly.access.add.MemRef_A3 = add nsw i64 %polly.access.mul.MemRef_A2, %22
+; CHECK-NEXT:   %polly.access.MemRef_A4 = getelementptr float, float addrspace(1)* %polly.access.cast.MemRef_A1, i64 %polly.access.add.MemRef_A3
+; CHECK-NEXT:   store float %p_tmp9, float addrspace(1)* %polly.access.MemRef_A4, align 4
 ; CHECK-NEXT:   %polly.indvar_next = add nsw i64 %polly.indvar, 1
 ; CHECK-NEXT:   %polly.loop_cond = icmp sle i64 %polly.indvar_next, 1
 ; CHECK-NEXT:   br i1 %polly.loop_cond, label %polly.loop_header, label %polly.loop_exit


