[llvm] r316871 - [X86][SSE] Split ComputeNumSignBits SEXT/AND/XOR/OR demandedelts test
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Oct 29 14:35:28 PDT 2017
Author: rksimon
Date: Sun Oct 29 14:35:28 2017
New Revision: 316871
URL: http://llvm.org/viewvc/llvm-project?rev=316871&view=rev
Log:
[X86][SSE] Split ComputeNumSignBits SEXT/AND/XOR/OR demandedelts test
Max depth was being exceeded which could prevent some combines working
Modified:
llvm/trunk/test/CodeGen/X86/known-signbits-vector.ll
Modified: llvm/trunk/test/CodeGen/X86/known-signbits-vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/known-signbits-vector.ll?rev=316871&r1=316870&r2=316871&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/known-signbits-vector.ll (original)
+++ llvm/trunk/test/CodeGen/X86/known-signbits-vector.ll Sun Oct 29 14:35:28 2017
@@ -276,8 +276,8 @@ define <2 x double> @signbits_ashr_conca
ret <2 x double> %6
}
-define float @signbits_ashr_sextinreg_bitops_extract_sitofp(<2 x i64> %a0, <2 x i64> %a1, i32 %a2) nounwind {
-; X32-LABEL: signbits_ashr_sextinreg_bitops_extract_sitofp:
+define float @signbits_ashr_sext_sextinreg_and_extract_sitofp(<2 x i64> %a0, <2 x i64> %a1, i32 %a2) nounwind {
+; X32-LABEL: signbits_ashr_sext_sextinreg_and_extract_sitofp:
; X32: # BB#0:
; X32-NEXT: pushl %ebp
; X32-NEXT: movl %esp, %ebp
@@ -300,9 +300,7 @@ define float @signbits_ashr_sextinreg_bi
; X32-NEXT: vpsrad $20, %xmm1, %xmm2
; X32-NEXT: vpsrlq $20, %xmm1, %xmm1
; X32-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
-; X32-NEXT: vpand %xmm1, %xmm0, %xmm2
-; X32-NEXT: vpor %xmm1, %xmm2, %xmm1
-; X32-NEXT: vpxor %xmm0, %xmm1, %xmm0
+; X32-NEXT: vpand %xmm1, %xmm0, %xmm0
; X32-NEXT: vmovq %xmm0, {{[0-9]+}}(%esp)
; X32-NEXT: fildll {{[0-9]+}}(%esp)
; X32-NEXT: fstps {{[0-9]+}}(%esp)
@@ -311,7 +309,7 @@ define float @signbits_ashr_sextinreg_bi
; X32-NEXT: popl %ebp
; X32-NEXT: retl
;
-; X64-LABEL: signbits_ashr_sextinreg_bitops_extract_sitofp:
+; X64-LABEL: signbits_ashr_sext_sextinreg_and_extract_sitofp:
; X64: # BB#0:
; X64-NEXT: vpsrlq $60, %xmm0, %xmm2
; X64-NEXT: vpsrlq $61, %xmm0, %xmm0
@@ -325,21 +323,71 @@ define float @signbits_ashr_sextinreg_bi
; X64-NEXT: vpsrad $20, %xmm1, %xmm2
; X64-NEXT: vpsrlq $20, %xmm1, %xmm1
; X64-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
+; X64-NEXT: vpand %xmm1, %xmm0, %xmm0
+; X64-NEXT: vmovq %xmm0, %rax
+; X64-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
+; X64-NEXT: retq
+ %1 = ashr <2 x i64> %a0, <i64 61, i64 60>
+ %2 = sext i32 %a2 to i64
+ %3 = insertelement <2 x i64> %a1, i64 %2, i32 0
+ %4 = shl <2 x i64> %3, <i64 20, i64 20>
+ %5 = ashr <2 x i64> %4, <i64 20, i64 20>
+ %6 = and <2 x i64> %1, %5
+ %7 = extractelement <2 x i64> %6, i32 0
+ %8 = sitofp i64 %7 to float
+ ret float %8
+}
+
+define float @signbits_ashr_sextvecinreg_bitops_extract_sitofp(<2 x i64> %a0, <4 x i32> %a1) nounwind {
+; X32-LABEL: signbits_ashr_sextvecinreg_bitops_extract_sitofp:
+; X32: # BB#0:
+; X32-NEXT: pushl %ebp
+; X32-NEXT: movl %esp, %ebp
+; X32-NEXT: andl $-8, %esp
+; X32-NEXT: subl $16, %esp
+; X32-NEXT: vmovdqa {{.*#+}} xmm2 = [0,2147483648,0,2147483648]
+; X32-NEXT: vpsrlq $60, %xmm2, %xmm3
+; X32-NEXT: vpsrlq $61, %xmm2, %xmm2
+; X32-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm3[4,5,6,7]
+; X32-NEXT: vpsrlq $60, %xmm0, %xmm3
+; X32-NEXT: vpsrlq $61, %xmm0, %xmm0
+; X32-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7]
+; X32-NEXT: vpxor %xmm2, %xmm0, %xmm0
+; X32-NEXT: vpsubq %xmm2, %xmm0, %xmm0
+; X32-NEXT: vpmovsxdq %xmm1, %xmm1
+; X32-NEXT: vpand %xmm1, %xmm0, %xmm2
+; X32-NEXT: vpor %xmm1, %xmm2, %xmm1
+; X32-NEXT: vpxor %xmm0, %xmm1, %xmm0
+; X32-NEXT: vmovq %xmm0, {{[0-9]+}}(%esp)
+; X32-NEXT: fildll {{[0-9]+}}(%esp)
+; X32-NEXT: fstps {{[0-9]+}}(%esp)
+; X32-NEXT: flds {{[0-9]+}}(%esp)
+; X32-NEXT: movl %ebp, %esp
+; X32-NEXT: popl %ebp
+; X32-NEXT: retl
+;
+; X64-LABEL: signbits_ashr_sextvecinreg_bitops_extract_sitofp:
+; X64: # BB#0:
+; X64-NEXT: vpsrlq $60, %xmm0, %xmm2
+; X64-NEXT: vpsrlq $61, %xmm0, %xmm0
+; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
+; X64-NEXT: vmovdqa {{.*#+}} xmm2 = [4,8]
+; X64-NEXT: vpxor %xmm2, %xmm0, %xmm0
+; X64-NEXT: vpsubq %xmm2, %xmm0, %xmm0
+; X64-NEXT: vpmovsxdq %xmm1, %xmm1
; X64-NEXT: vpand %xmm1, %xmm0, %xmm2
; X64-NEXT: vpor %xmm1, %xmm2, %xmm1
; X64-NEXT: vpxor %xmm0, %xmm1, %xmm0
; X64-NEXT: vmovq %xmm0, %rax
; X64-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
; X64-NEXT: retq
- %1 = ashr <2 x i64> %a0, <i64 61, i64 60>
- %2 = sext i32 %a2 to i64
- %3 = insertelement <2 x i64> %a1, i64 %2, i32 0
- %4 = shl <2 x i64> %3, <i64 20, i64 20>
- %5 = ashr <2 x i64> %4, <i64 20, i64 20>
- %6 = and <2 x i64> %1, %5
- %7 = or <2 x i64> %6, %5
- %8 = xor <2 x i64> %7, %1
- %9 = extractelement <2 x i64> %8, i32 0
- %10 = sitofp i64 %9 to float
- ret float %10
+ %1 = ashr <2 x i64> %a0, <i64 61, i64 60>
+ %2 = shufflevector <4 x i32> %a1, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
+ %3 = sext <2 x i32> %2 to <2 x i64>
+ %4 = and <2 x i64> %1, %3
+ %5 = or <2 x i64> %4, %3
+ %6 = xor <2 x i64> %5, %1
+ %7 = extractelement <2 x i64> %6, i32 0
+ %8 = sitofp i64 %7 to float
+ ret float %8
}
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