[PATCH] D37798: Teach TargetInstrInfo::getInlineAsmLength to parse .space directives with integer arguments

[Alex Bradbury via Phabricator via llvm-commits]

asb created this revision.
Herald added subscribers: kristof.beyls, arichardson, tpr, aemerson.

It's currently quite difficult to test passes like branch relaxation, which requires branches with large displacement to be generated. The .space assembler directive makes it easy to create arbitrarily large basic blocks, but getInlineAsmLength is not able to parse it and so the size of the block is not correctly estimated. Other backends (AArch64, AMDGPU) introduce options just for testing that artificially restrict the ranges of branch instructions (e.g. aarch64-tbz-offset-bits). Although parsing a single form of the .space directive feels inelegant, it does allow a more direct testing approach.

This patch adapts the .space parsing code from Mips16InstrInfo::getInlineAsmLength and removes it now the extra functionality is provided by the base implementation. CC @fhahn, @rengolin as this change might motivate dropping aarch64-{tbz,cbz,bcc}-offset-bits and updating the tests to use .space. I want to move this functionality to the generic getInlineAsmLength as 1) I need the same for RISC-V, and 2) I feel other backends will benefit from more direct testing of large branch displacements.


https://reviews.llvm.org/D37798

Files:
  lib/CodeGen/TargetInstrInfo.cpp
  lib/Target/Mips/Mips16InstrInfo.cpp
  lib/Target/Mips/Mips16InstrInfo.h

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