[PATCH] D37654: PPC: Don't select lxv/stxv for insufficiently aligned stack slots.

[Hal Finkel via llvm-commits]

On 09/11/2017 06:45 PM, Kyle Butt wrote:
> No, it failed to emit any code. The frame index fixup code scavenges a 
> Register to materialize the offset. Nothing reserves an emergency 
> spill slot for the scavenging. Boom!
>
> I'm thinking of adjusting the slot to be sufficiently aligned.

That also seems reasonable (although the the correctness fix seems good 
regardless).

  -Hal

>
> On Sep 9, 2017 1:46 AM, "Nemanja Ivanovic" <nemanja.i.ibm at gmail.com 
> <mailto:nemanja.i.ibm at gmail.com>> wrote:
>
>     Ah, OK good. So I imagine it failed the machine verifier.
>     That's good - as long as we don't emit bad code :)
>
>     On Sat, Sep 9, 2017 at 9:54 AM, Eric Christopher
>     <echristo at gmail.com <mailto:echristo at gmail.com>> wrote:
>
>         It failed in the register scavenger :)
>
>
>         On Fri, Sep 8, 2017, 11:46 PM Nemanja Ivanovic via Phabricator
>         <reviews at reviews.llvm.org <mailto:reviews at reviews.llvm.org>>
>         wrote:
>
>             nemanjai added a comment.
>
>             I imagine this patch was prompted by a bug. Just out of
>             curiosity, did the assert:
>
>               assert(MO.isImm() && !(MO.getImm() % 16) &&
>                      "Expecting an immediate that is a multiple of 16");
>
>             fire for the case where the frame op was lowered to an
>             lxv/stxv with an offset that isn't a multiple of 16? If
>             not, perhaps we need another assert somewhere else?
>
>
>             Repository:
>               rL LLVM
>
>             https://reviews.llvm.org/D37654
>             <https://reviews.llvm.org/D37654>
>
>
>
>

-- 
Hal Finkel
Lead, Compiler Technology and Programming Languages
Leadership Computing Facility
Argonne National Laboratory

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