[llvm] r306414 - Updated and extended the information about each instruction in HSW and SNB to include the following data:
Chandler Carruth via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 28 03:19:32 PDT 2017
This commit cites a Phabricator revision that never actually went to
'llvm-commits' for review. Further, that revision never got a final LGTM
and I pointed out several issues with this commit on Phabricator before
realizing it wasn't even going to the full list. Here is the response I
sent to Phab:
----
While the work here is pretty great, you were asked to wait for someone
else to LGTM and you didn't. That's really poor form. There are plenty of
issues here that really should be addressed before this was landed. Please
revert and start looking at them.
1) The commit message is very poorly formated and doesn't actually describe
the kinds of differences that people should expect.
2) There are *numerous* substantial changes to the tests that are
completely unrelated to this patch. For example, see the 'half.ll' test
case. Please update the FileCheck lines for tests you need to modify in a
NFC patch that *just* gives you a clean baseline so that the only thing
changing here are the scheduling differences. this is especially important
considering how many tests are changed and in how many ways.
3) This gives a very significant new influx of data to the scheduler. I'm
actually really excited about that. However, even looking at thet test
cases updated, I see substantially different instruction sequences. What
testing have you done to ensure this is correct? We have at least one
internal user (based on Halide) that sees correctness regressions after
this commit. It may not be this commit that has the bug, but if we have
latent missing constraints on instructions (which we probably do) massive
changes to the scheduler are likely to expose bugs. It may be worth
discussing in the change what testing has been done and ask others to help
test such a large change as this.
Thanks,
-Chandler
----
Given that the review didn't even happen on the list, and that we have some
indications that this *is* uncovering some latent issues in the x86 backend
(missing constraints that now show up due to scheduler changes likely?)
I've asked folks to go ahead and revert this until it gets sorted out.
-Chandler
On Tue, Jun 27, 2017 at 8:05 AM Gadi Haber via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
> Author: gadi.haber
> Date: Tue Jun 27 08:05:13 2017
> New Revision: 306414
>
> URL: http://llvm.org/viewvc/llvm-project?rev=306414&view=rev
> Log:
> Updated and extended the information about each instruction in HSW and SNB
> to include the following data:
> •static latency
> •number of uOps from which the instructions consists
> •all ports used by the instruction
>
> Reviewers:
> RKSimon
> zvi
> aymanmus
> m_zuckerman
>
> Differential Revision: https://reviews.llvm.org/D33897
>
>
> Modified:
> llvm/trunk/lib/Target/X86/X86SchedHaswell.td
> llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
> llvm/trunk/test/CodeGen/X86/avx-schedule.ll
> llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll
> llvm/trunk/test/CodeGen/X86/avx2-schedule.ll
> llvm/trunk/test/CodeGen/X86/avx2-vector-shifts.ll
> llvm/trunk/test/CodeGen/X86/avx512-cmp.ll
> llvm/trunk/test/CodeGen/X86/avx512-cvt.ll
> llvm/trunk/test/CodeGen/X86/avx512-insert-extract.ll
> llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.ll
> llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll
> llvm/trunk/test/CodeGen/X86/avx512-vec-cmp.ll
> llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
> llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll
> llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-256.ll
>
> llvm/trunk/test/CodeGen/X86/extractelement-legalization-store-ordering.ll
> llvm/trunk/test/CodeGen/X86/fp128-i128.ll
> llvm/trunk/test/CodeGen/X86/gather-addresses.ll
> llvm/trunk/test/CodeGen/X86/half.ll
> llvm/trunk/test/CodeGen/X86/illegal-bitfield-loadstore.ll
> llvm/trunk/test/CodeGen/X86/mul-constant-i32.ll
> llvm/trunk/test/CodeGen/X86/mul-constant-i64.ll
> llvm/trunk/test/CodeGen/X86/pr32329.ll
> llvm/trunk/test/CodeGen/X86/recip-fastmath.ll
> llvm/trunk/test/CodeGen/X86/recip-fastmath2.ll
> llvm/trunk/test/CodeGen/X86/sse-schedule.ll
> llvm/trunk/test/CodeGen/X86/sse2-schedule.ll
> llvm/trunk/test/CodeGen/X86/sse3-schedule.ll
> llvm/trunk/test/CodeGen/X86/sse41-schedule.ll
> llvm/trunk/test/CodeGen/X86/sse42-schedule.ll
> llvm/trunk/test/CodeGen/X86/ssse3-schedule.ll
> llvm/trunk/test/CodeGen/X86/vector-shift-ashr-512.ll
> llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v32.ll
>
> Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=306414&r1=306413&r2=306414&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
> +++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Tue Jun 27 08:05:13 2017
> @@ -23,8 +23,8 @@ def HaswellModel : SchedMachineModel {
> // Based on the LSD (loop-stream detector) queue size and benchmarking
> data.
> let LoopMicroOpBufferSize = 50;
>
> - // FIXME: SSE4 and AVX are unimplemented. This flag is set to allow
> - // the scheduler to assign a default model to unrecognized opcodes.
> + // This flag is set to allow the scheduler to assign a default model to
> + // unrecognized opcodes.
> let CompleteModel = 0;
> }
>
> @@ -267,1914 +267,3251 @@ def : WriteRes<WriteMicrocoded, [HWPort0
> def : WriteRes<WriteFence, [HWPort23, HWPort4]>;
> def : WriteRes<WriteNop, []>;
>
> -//================ Exceptions ================//
> -
> -//-- Specific Scheduling Models --//
> -
> -// Starting with P0.
> -def WriteP0 : SchedWriteRes<[HWPort0]>;
> -
> -def WriteP0_P1_Lat4 : SchedWriteRes<[HWPort0, HWPort1]> {
> - let Latency = 4;
> - let NumMicroOps = 2;
> - let ResourceCycles = [1, 1];
> -}
>
> +////////////////////////////////////////////////////////////////////////////////
> +// Horizontal add/sub instructions.
>
> +////////////////////////////////////////////////////////////////////////////////
>
> -def WriteP0_P1_Lat4Ld : SchedWriteRes<[HWPort0, HWPort1, HWPort23]> {
> - let Latency = 8;
> +// HADD, HSUB PS/PD
> +// x,x / v,v,v.
> +def : WriteRes<WriteFHAdd, [HWPort1, HWPort5]> {
> + let Latency = 5;
> let NumMicroOps = 3;
> - let ResourceCycles = [1, 1, 1];
> + let ResourceCycles = [1, 2];
> }
>
> -def WriteP01 : SchedWriteRes<[HWPort01]>;
> +// x,m / v,v,m.
> +def : WriteRes<WriteFHAddLd, [HWPort1, HWPort5, HWPort23]> {
> + let Latency = 9;
> + let NumMicroOps = 4;
> + let ResourceCycles = [1, 2, 1];
> +}
>
> -def Write2P01 : SchedWriteRes<[HWPort01]> {
> - let NumMicroOps = 2;
> +// PHADD|PHSUB (S) W/D.
> +// v <- v,v.
> +def : WriteRes<WritePHAdd, [HWPort1, HWPort5]> {
> + let Latency = 3;
> + let NumMicroOps = 3;
> + let ResourceCycles = [1, 2];
> }
> -def Write3P01 : SchedWriteRes<[HWPort01]> {
> +// v <- v,m.
> +def : WriteRes<WritePHAddLd, [HWPort1, HWPort5, HWPort23]> {
> + let Latency = 6;
> let NumMicroOps = 3;
> + let ResourceCycles = [1, 2, 1];
> }
>
> -def WriteP015 : SchedWriteRes<[HWPort015]>;
> +// Remaining instrs.
>
> -def WriteP01_P5 : SchedWriteRes<[HWPort01, HWPort5]> {
> - let NumMicroOps = 2;
> +def HWWriteResGroup0 : SchedWriteRes<[HWPort23]> {
> + let Latency = 0;
> + let NumMicroOps = 1;
> + let ResourceCycles = [1];
> }
> -def WriteP06 : SchedWriteRes<[HWPort06]>;
> +def: InstRW<[HWWriteResGroup0], (instregex "LDDQUrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "MMX_MOVD64from64rm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "MMX_MOVD64rm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "MMX_MOVD64to64rm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "MMX_MOVQ64rm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "MOV32rm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "MOV64toPQIrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "MOV8rm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "MOVAPDrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "MOVAPSrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "MOVDDUPrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "MOVDI2PDIrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "MOVDQArm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "MOVDQUrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "MOVNTDQArm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "MOVSHDUPrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "MOVSLDUPrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "MOVSSrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "MOVSX32rm16")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "MOVSX32rm8")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "MOVUPDrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "MOVUPSrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "MOVZX32rm16")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "MOVZX32rm8")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "PREFETCHNTA")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "PREFETCHT0")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "PREFETCHT1")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "PREFETCHT2")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VBROADCASTF128")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VBROADCASTI128")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VBROADCASTSDYrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VBROADCASTSSrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VBROADCASTSSrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VLDDQUYrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VLDDQUrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VMOV64toPQIrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VMOVAPDYrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VMOVAPDrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VMOVAPSYrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VMOVAPSrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VMOVDDUPYrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VMOVDDUPrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VMOVDI2PDIrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VMOVDQAYrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VMOVDQArm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VMOVDQUYrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VMOVDQUrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VMOVNTDQAYrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VMOVNTDQArm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VMOVQI2PQIrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VMOVSDrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VMOVSHDUPYrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VMOVSHDUPrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VMOVSLDUPYrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VMOVSLDUPrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VMOVSSrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VMOVUPDYrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VMOVUPDrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VMOVUPSYrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VMOVUPSrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VPBROADCASTDYrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VPBROADCASTDrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VPBROADCASTQYrm")>;
> +def: InstRW<[HWWriteResGroup0], (instregex "VPBROADCASTQrm")>;
> +
> +def HWWriteResGroup1 : SchedWriteRes<[HWPort4,HWPort237]> {
> + let Latency = 0;
> + let NumMicroOps = 2;
> + let ResourceCycles = [1,1];
> +}
> +def: InstRW<[HWWriteResGroup1], (instregex "MMX_MOVD64from64rm")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "MMX_MOVD64mr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "MMX_MOVNTQmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "MMX_MOVQ64mr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "MOV64mr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "MOV8mi")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "MOV8mr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "MOVAPDmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "MOVAPSmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "MOVDQAmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "MOVDQUmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "MOVHPDmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "MOVHPSmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "MOVLPDmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "MOVLPSmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "MOVNTDQmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "MOVNTI_64mr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "MOVNTImr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "MOVNTPDmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "MOVNTPSmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "MOVPDI2DImr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "MOVPQI2QImr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "MOVPQIto64mr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "MOVSSmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "MOVUPDmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "MOVUPSmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VEXTRACTF128mr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VEXTRACTI128mr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVAPDYmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVAPDmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVAPSYmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVAPSmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVDQAYmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVDQAmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVDQUYmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVDQUmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVHPDmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVHPSmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVLPDmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVLPSmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTDQYmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTDQmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTPDYmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTPDmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTPSYmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTPSmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVPDI2DImr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVPQI2QImr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVPQIto64mr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVSDmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVSSmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVUPDYmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVUPDmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVUPSYmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMOVUPSmr")>;
> +def: InstRW<[HWWriteResGroup1], (instregex "VMPTRSTm")>;
>
> -def Write2P06 : SchedWriteRes<[HWPort06]> {
> +def HWWriteResGroup2 : SchedWriteRes<[HWPort0]> {
> let Latency = 1;
> - let NumMicroOps = 2;
> - let ResourceCycles = [2];
> + let NumMicroOps = 1;
> + let ResourceCycles = [1];
> }
> +def: InstRW<[HWWriteResGroup2], (instregex "MMX_MOVD64from64rr")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "MMX_MOVD64grr")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PMOVMSKBrr")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLDri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLDrr")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLQri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLQrr")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLWri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLWrr")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRADri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRADrr")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRAWri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRAWrr")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLDri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLDrr")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLQri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLQrr")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLWri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLWrr")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "MOVPDI2DIrr")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "MOVPQIto64rr")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "PSLLDri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "PSLLQri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "PSLLWri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "PSRADri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "PSRAWri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "PSRLDri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "PSRLQri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "PSRLWri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VMOVPDI2DIrr")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VMOVPQIto64rr")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VPSLLDri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VPSLLDrm")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VPSLLQri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VPSLLQrm")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VPSLLVQYrr")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VPSLLVQrr")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VPSLLWri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VPSLLWrm")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VPSRADYri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VPSRADri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VPSRAWYri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VPSRAWri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VPSRLDYri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VPSRLDri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VPSRLQYri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VPSRLQri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VPSRLVQYrr")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VPSRLVQrr")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VPSRLWYri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VPSRLWri")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VTESTPDYrr")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VTESTPDrr")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VTESTPSYrr")>;
> +def: InstRW<[HWWriteResGroup2], (instregex "VTESTPSrr")>;
>
> -def Write3P06_Lat2 : SchedWriteRes<[HWPort06]> {
> - let Latency = 2;
> - let NumMicroOps = 3;
> - let ResourceCycles = [3];
> +def HWWriteResGroup3 : SchedWriteRes<[HWPort1]> {
> + let Latency = 1;
> + let NumMicroOps = 1;
> + let ResourceCycles = [1];
> }
> +def: InstRW<[HWWriteResGroup3], (instregex "MASKMOVDQU64")>;
> +def: InstRW<[HWWriteResGroup3], (instregex "MMX_MASKMOVQ64")>;
>
> -def WriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
> - let NumMicroOps = 2;
> +def HWWriteResGroup4 : SchedWriteRes<[HWPort5]> {
> + let Latency = 1;
> + let NumMicroOps = 1;
> + let ResourceCycles = [1];
> }
> +def: InstRW<[HWWriteResGroup4], (instregex "ANDNPDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "ANDNPSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "ANDPDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "ANDPSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "INSERTPSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "KORTESTBrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVD64rr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVD64to64rr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVQ2DQrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "MMX_PALIGNR64irr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "MMX_PSHUFBrr64")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "MMX_PSHUFWri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKHBWirr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKHDQirr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKHWDirr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKLBWirr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKLDQirr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKLWDirr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "MOV64toPQIrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "MOVAPDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "MOVAPSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "MOVDDUPrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "MOVDI2PDIrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "MOVHLPSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "MOVLHPSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "MOVSDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "MOVSHDUPrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "MOVSLDUPrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "MOVSSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "MOVUPDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "MOVUPSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "ORPDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "ORPSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PACKSSDWrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PACKSSWBrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PACKUSDWrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PACKUSWBrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PALIGNRrri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PBLENDWrri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXBDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXBQrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXBWrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXDQrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXWDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXWQrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXBDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXBQrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXBWrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXDQrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXWDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXWQrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PSHUFBrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PSHUFDri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PSHUFHWri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PSHUFLWri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PSLLDQri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PSRLDQri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKHBWrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKHDQrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKHQDQrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKHWDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKLBWrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKLDQrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKLQDQrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKLWDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "SHUFPDrri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "SHUFPSrri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "UNPCKHPDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "UNPCKHPSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "UNPCKLPDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "UNPCKLPSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VANDNPDYrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VANDNPDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VANDNPSYrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VANDNPSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VANDPDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VANDPDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VANDPSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VBROADCASTSSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VGATHERQPSZrm")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VINSERTPSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VMOV64toPQIrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VMOV64toPQIrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPDYrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPSYrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VMOVDDUPYrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VMOVDDUPrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VMOVHLPSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VMOVLHPSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VMOVSDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VMOVSHDUPYrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VMOVSHDUPrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VMOVSLDUPYrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VMOVSLDUPrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VMOVSSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPDYrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPSYrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VORPDYrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VORPDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VORPSYrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VORPSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPACKSSDWYrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPACKSSDWrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPACKSSWBYrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPACKSSWBrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPACKUSDWYrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPACKUSDWrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPACKUSWBYrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPACKUSWBrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPALIGNRYrri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPALIGNRrri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPBLENDWYrri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPBLENDWrri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPBROADCASTDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPBROADCASTQrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPDri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPDrm")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPSri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPSrm")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXBDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXBQrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXBWrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXDQrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXWDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXWQrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXBDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXBQrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXBWrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXDQrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXWDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXWQrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFBrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFBrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFDYri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFDri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFHWri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFLWYri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFLWri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPSLLDQYri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPSLLDQri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPSRLDQYri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPSRLDQri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHBWYrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHBWrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHDQYrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHDQrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHQDQrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHWDYrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHWDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLBWrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLDQYrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLDQrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLQDQYrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLQDQrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLWDYrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLWDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VSHUFPDYrri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VSHUFPDrri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VSHUFPSYrri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VSHUFPSrri")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKHPDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKHPSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKLPDYrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKLPDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKLPSYrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKLPSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VXORPDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "VXORPSrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "XORPDrr")>;
> +def: InstRW<[HWWriteResGroup4], (instregex "XORPSrr")>;
>
> -def Write2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
> - let NumMicroOps = 3;
> - let ResourceCycles = [2, 1];
> +def HWWriteResGroup5 : SchedWriteRes<[HWPort6]> {
> + let Latency = 1;
> + let NumMicroOps = 1;
> + let ResourceCycles = [1];
> }
> +def: InstRW<[HWWriteResGroup5], (instregex "JMP64r")>;
>
> -def Write2P0156_Lat2 : SchedWriteRes<[HWPort0156]> {
> - let Latency = 2;
> - let ResourceCycles = [2];
> -}
> -def Write2P0156_Lat2Ld : SchedWriteRes<[HWPort0156, HWPort23]> {
> - let Latency = 6;
> - let ResourceCycles = [2, 1];
> +def HWWriteResGroup6 : SchedWriteRes<[HWPort01]> {
> + let Latency = 1;
> + let NumMicroOps = 1;
> + let ResourceCycles = [1];
> }
> +def: InstRW<[HWWriteResGroup6], (instregex "FINCSTP")>;
> +def: InstRW<[HWWriteResGroup6], (instregex "FNOP")>;
>
> -def Write5P0156 : SchedWriteRes<[HWPort0156]> {
> - let NumMicroOps = 5;
> - let ResourceCycles = [5];
> +def HWWriteResGroup7 : SchedWriteRes<[HWPort0]> {
> + let Latency = 1;
> + let NumMicroOps = 1;
> + let ResourceCycles = [1];
> }
> +def: InstRW<[HWWriteResGroup7], (instregex "BT32ri8")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "BT32rr")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "BTC32ri8")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "BTC32rr")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "BTR32ri8")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "BTR32rr")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "BTS32ri8")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "BTS32rr")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "CDQ")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "CQO")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "RORX32ri")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "RORX64ri")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SAR32ri")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SAR64r1")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SAR8r1")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SAR8ri")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SARX32rr")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SARX64rr")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SETAEr")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SETBr")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SETEr")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SETGEr")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SETGr")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SETLEr")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SETLr")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SETNEr")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SETNOr")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SETNPr")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SETNSr")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SETOr")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SETPr")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SETSr")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SHL32ri")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SHL64r1")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SHL8r1")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SHL8ri")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SHLX32rr")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SHLX64rr")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SHR32ri")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SHR64r1")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SHR8r1")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SHR8ri")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SHRX32rr")>;
> +def: InstRW<[HWWriteResGroup7], (instregex "SHRX64rr")>;
>
> -def WriteP0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]>
> {
> +def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> {
> let Latency = 1;
> - let ResourceCycles = [1, 2, 1];
> + let NumMicroOps = 1;
> + let ResourceCycles = [1];
> }
> +def: InstRW<[HWWriteResGroup8], (instregex "ANDN32rr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "ANDN64rr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "BLSI32rr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "BLSI64rr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "BLSMSK32rr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "BLSMSK64rr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "BLSR32rr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "BLSR64rr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "BZHI32rr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "BZHI64rr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "LEA64_32r")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSBrr64")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSDrr64")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSWrr64")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDBirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDDirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDQirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDSBirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDSWirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDUSBirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDUSWirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDWirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PAVGBirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PAVGWirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPEQBirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPEQDirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPEQWirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPGTBirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPGTDirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPGTWirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PMAXSWirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PMAXUBirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PMINSWirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PMINUBirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSIGNBrr64")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSIGNDrr64")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSIGNWrr64")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBBirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBDirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBQirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBSBirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBSWirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBUSBirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBUSWirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBWirr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PABSBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PABSDrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PABSWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PADDBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PADDDrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PADDQrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PADDSBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PADDSWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PADDUSBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PADDUSWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PADDWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PAVGBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PAVGWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PCMPEQBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PCMPEQDrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PCMPEQQrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PCMPEQWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PCMPGTBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PCMPGTDrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PCMPGTWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PMAXSBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PMAXSDrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PMAXSWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PMAXUBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PMAXUDrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PMAXUWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PMINSBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PMINSDrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PMINSWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PMINUBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PMINUDrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PMINUWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PSIGNBrr128")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PSIGNDrr128")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PSIGNWrr128")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PSUBBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PSUBDrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PSUBQrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PSUBSBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PSUBSWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PSUBUSBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PSUBUSWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "PSUBWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VMASKMOVPSYrm")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPABSBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPABSBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPABSDYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPABSDrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPABSWYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPABSWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPADDBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPADDBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPADDDrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPADDDrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPADDQYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPADDQrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPADDSBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPADDSWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPADDUSBYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPADDUSBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPADDUSWYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPADDUSWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPADDWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPAVGBYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPAVGBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPAVGWYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPAVGWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQDrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQDrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQQrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTBYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTDYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTDrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTWYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSBYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSDYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSDrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSWYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUBYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUDYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUDrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUWYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPMINSBYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPMINSBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPMINSDYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPMINSDrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPMINSWYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPMINSWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPMINUBYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPMINUBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPMINUDYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPMINUDrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPMINUWYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPMINUWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNBYrr256")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNBrr128")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNDYrr256")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNDrr128")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNWYrr256")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNWrr128")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBBYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBDYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBDrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBQYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBQrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBSBYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBSBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBSWYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBSWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBUSBYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBUSBrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBUSWYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBUSWrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBWYrr")>;
> +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBWrr")>;
>
> -def Write2P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237,
> HWPort4]> {
> +def HWWriteResGroup9 : SchedWriteRes<[HWPort015]> {
> let Latency = 1;
> - let ResourceCycles = [2, 2, 1];
> + let NumMicroOps = 1;
> + let ResourceCycles = [1];
> }
> +def: InstRW<[HWWriteResGroup9], (instregex "BLENDPDrri")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "BLENDPSrri")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "MMX_MOVD64from64rr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "MMX_MOVQ64rr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "MMX_PANDNirr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "MMX_PANDirr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "MMX_PORirr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "MMX_PXORirr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "MOVDQArr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "MOVDQUrr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "MOVPQI2QIrr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "PANDNrr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "PANDrr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "PORrr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "PXORrr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "VBLENDPDYrri")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "VBLENDPDrri")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "VBLENDPSYrri")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "VBLENDPSrri")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQAYrr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQArr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQUYrr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQUrr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "VMOVPQI2QIrr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "VMOVZPQILo2PQIrr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "VPANDNYrr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "VPANDNrr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "VPANDYrr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "VPANDrr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "VPBLENDDYrri")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "VPBLENDDrri")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "VPORYrr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "VPORrr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "VPXORYrr")>;
> +def: InstRW<[HWWriteResGroup9], (instregex "VPXORrr")>;
>
> -def Write3P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237,
> HWPort4]> {
> +def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> {
> let Latency = 1;
> - let ResourceCycles = [3, 2, 1];
> + let NumMicroOps = 1;
> + let ResourceCycles = [1];
> }
> +def: InstRW<[HWWriteResGroup10], (instregex "ADD32ri8")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "ADD32rr")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "ADD8ri")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "ADD8rr")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "AND32ri")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "AND64ri8")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "AND64rr")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "AND8ri")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "AND8rr")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "CBW")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "CLC")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "CMC")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "CMP16ri8")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "CMP32i32")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "CMP64rr")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "CMP8ri")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "CMP8rr")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "CWDE")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "DEC64r")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "DEC8r")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "INC64r")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "INC8r")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "LAHF")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "MOV32rr")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "MOV8ri")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "MOV8rr")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "MOVSX32rr16")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "MOVSX32rr8")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "MOVZX32rr16")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "MOVZX32rr8")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "NEG64r")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "NEG8r")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "NOOP")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "NOT64r")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "NOT8r")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "OR64ri8")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "OR64rr")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "OR8ri")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "OR8rr")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "SAHF")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "SGDT64m")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "SIDT64m")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "SLDT16m")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "SMSW16m")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "STC")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "STRm")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "SUB64ri8")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "SUB64rr")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "SUB8ri")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "SUB8rr")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "SYSCALL")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "TEST64rr")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "TEST8ri")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "TEST8rr")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "XCHG64rr")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "XOR32rr")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "XOR64ri8")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "XOR8ri")>;
> +def: InstRW<[HWWriteResGroup10], (instregex "XOR8rr")>;
>
> -// Starting with P1.
> -def WriteP1 : SchedWriteRes<[HWPort1]>;
> -
> -def WriteP1_P23 : SchedWriteRes<[HWPort1, HWPort23]> {
> +def HWWriteResGroup11 : SchedWriteRes<[HWPort0,HWPort23]> {
> + let Latency = 1;
> let NumMicroOps = 2;
> + let ResourceCycles = [1,1];
> }
> -def WriteP1_Lat3 : SchedWriteRes<[HWPort1]> {
> - let Latency = 3;
> -}
> -def WriteP1_Lat3Ld : SchedWriteRes<[HWPort1, HWPort23]> {
> - let Latency = 7;
> -}
> +def: InstRW<[HWWriteResGroup11], (instregex "CVTPS2PDrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "CVTSS2SDrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSLLDrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSLLQrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSLLWrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSRADrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSRAWrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSRLDrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSRLQrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSRLWrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "VCVTPH2PSYrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "VCVTPH2PSrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "VCVTPS2PDrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "VCVTSS2SDrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "VPSLLDYri")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "VPSLLQYri")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "VPSLLVQYrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "VPSLLVQrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "VPSLLWYri")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "VPSRADYrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "VPSRAWYrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "VPSRLDYrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "VPSRLQYrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "VPSRLVQYrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "VPSRLVQrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "VPSRLWYrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "VTESTPDYrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "VTESTPDrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "VTESTPSYrm")>;
> +def: InstRW<[HWWriteResGroup11], (instregex "VTESTPSrm")>;
>
> -def Write2P1 : SchedWriteRes<[HWPort1]> {
> +def HWWriteResGroup12 : SchedWriteRes<[HWPort5,HWPort23]> {
> + let Latency = 1;
> let NumMicroOps = 2;
> - let ResourceCycles = [2];
> -}
> -def Write2P1_P23 : SchedWriteRes<[HWPort1, HWPort23]> {
> - let NumMicroOps = 3;
> - let ResourceCycles = [2, 1];
> -}
> -def WriteP15 : SchedWriteRes<[HWPort15]>;
> -def WriteP15Ld : SchedWriteRes<[HWPort15, HWPort23]> {
> - let Latency = 4;
> + let ResourceCycles = [1,1];
> }
> +def: InstRW<[HWWriteResGroup12], (instregex "ANDNPDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "ANDNPSrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "ANDPDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "ANDPSrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "INSERTPSrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "MMX_PALIGNR64irm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "MMX_PINSRWirmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "MMX_PSHUFBrm64")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "MMX_PSHUFWmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "MMX_PUNPCKHBWirm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "MMX_PUNPCKHDQirm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "MMX_PUNPCKHWDirm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "MMX_PUNPCKLBWirm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "MMX_PUNPCKLDQirm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "MMX_PUNPCKLWDirm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "MOVHPDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "MOVHPSrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "MOVLPDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "MOVLPSrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "ORPDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "ORPSrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PACKSSDWrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PACKSSWBrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PACKUSDWrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PACKUSWBrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PALIGNRrmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PBLENDWrmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PINSRBrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PINSRDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PINSRQrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PINSRWrmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PMOVSXBDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PMOVSXBQrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PMOVSXBWrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PMOVSXDQrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PMOVSXWDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PMOVSXWQrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PMOVZXBDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PMOVZXBQrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PMOVZXBWrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PMOVZXDQrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PMOVZXWDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PMOVZXWQrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PSHUFBrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PSHUFDmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PSHUFHWmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PSHUFLWmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PUNPCKHBWrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PUNPCKHDQrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PUNPCKHQDQrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PUNPCKHWDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PUNPCKLBWrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PUNPCKLDQrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PUNPCKLQDQrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "PUNPCKLWDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "SHUFPDrmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "SHUFPSrmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "UNPCKHPDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "UNPCKHPSrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "UNPCKLPDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "UNPCKLPSrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VANDNPDYrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VANDNPDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VANDNPSYrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VANDNPSrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VANDPDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VANDPDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VANDPSrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VANDPSrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VINSERTPSrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VMOVHPDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VMOVHPSrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VMOVLPDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VMOVLPSrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VORPDYrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VORPDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VORPSYrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VORPSrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPACKSSDWYrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPACKSSDWrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPACKSSWBYrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPACKSSWBrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPACKUSDWYrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPACKUSDWrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPACKUSWBYrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPACKUSWBrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPALIGNRYrmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPALIGNRrmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPBLENDWYrmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPBLENDWrmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPERMILPDYri")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPERMILPDmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPERMILPDmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPERMILPDri")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPERMILPSYri")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPERMILPSmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPERMILPSmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPERMILPSri")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPINSRBrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPINSRDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPINSRQrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPINSRWrmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPMOVSXBDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPMOVSXBQrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPMOVSXBWrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPMOVSXDQrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPMOVSXWDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPMOVSXWQrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPMOVZXBDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPMOVZXBQrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPMOVZXBWrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPMOVZXDQrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPMOVZXWDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPMOVZXWQrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPSHUFBrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPSHUFBrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPSHUFDYmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPSHUFDmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPSHUFHWmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPSHUFHWmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPSHUFLWYmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPSHUFLWmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKHBWYrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKHBWrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKHDQYrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKHDQrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKHQDQrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKHQDQrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKHWDYrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKHWDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKLBWrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKLBWrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKLDQYrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKLDQrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKLQDQYrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKLQDQrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKLWDYrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKLWDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VSHUFPDYrmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VSHUFPDrmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VSHUFPSYrmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VSHUFPSrmi")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VUNPCKHPDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VUNPCKHPDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VUNPCKHPSrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VUNPCKHPSrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VUNPCKLPDYrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VUNPCKLPDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VUNPCKLPSYrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VUNPCKLPSrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VXORPDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VXORPDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VXORPSrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "VXORPSrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "XORPDrm")>;
> +def: InstRW<[HWWriteResGroup12], (instregex "XORPSrm")>;
>
> -def WriteP1_P5_Lat4 : SchedWriteRes<[HWPort1, HWPort5]> {
> - let Latency = 4;
> +def HWWriteResGroup13 : SchedWriteRes<[HWPort6,HWPort23]> {
> + let Latency = 1;
> let NumMicroOps = 2;
> - let ResourceCycles = [1, 1];
> + let ResourceCycles = [1,1];
> }
> +def: InstRW<[HWWriteResGroup13], (instregex "FARJMP64")>;
> +def: InstRW<[HWWriteResGroup13], (instregex "JMP64m")>;
>
> -def WriteP1_P5_Lat4Ld : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> {
> - let Latency = 8;
> - let NumMicroOps = 3;
> - let ResourceCycles = [1, 1, 1];
> +def HWWriteResGroup14 : SchedWriteRes<[HWPort23,HWPort0]> {
> + let Latency = 1;
> + let NumMicroOps = 2;
> + let ResourceCycles = [1,1];
> }
> +def: InstRW<[HWWriteResGroup14], (instregex "BT64mi8")>;
> +def: InstRW<[HWWriteResGroup14], (instregex "RORX32mi")>;
> +def: InstRW<[HWWriteResGroup14], (instregex "RORX64mi")>;
> +def: InstRW<[HWWriteResGroup14], (instregex "SARX32rm")>;
> +def: InstRW<[HWWriteResGroup14], (instregex "SARX64rm")>;
> +def: InstRW<[HWWriteResGroup14], (instregex "SHLX32rm")>;
> +def: InstRW<[HWWriteResGroup14], (instregex "SHLX64rm")>;
> +def: InstRW<[HWWriteResGroup14], (instregex "SHRX32rm")>;
> +def: InstRW<[HWWriteResGroup14], (instregex "SHRX64rm")>;
>
> -def WriteP1_P5_Lat6 : SchedWriteRes<[HWPort1, HWPort5]> {
> - let Latency = 6;
> +def HWWriteResGroup15 : SchedWriteRes<[HWPort23,HWPort15]> {
> + let Latency = 1;
> let NumMicroOps = 2;
> - let ResourceCycles = [1, 1];
> + let ResourceCycles = [1,1];
> }
> +def: InstRW<[HWWriteResGroup15], (instregex "ANDN32rm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "ANDN64rm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "BLSI32rm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "BLSI64rm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "BLSMSK32rm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "BLSMSK64rm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "BLSR32rm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "BLSR64rm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "BZHI32rm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "BZHI64rm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PABSBrm64")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PABSDrm64")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PABSWrm64")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PADDBirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PADDDirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PADDQirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PADDSBirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PADDSWirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PADDUSBirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PADDUSWirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PADDWirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PAVGBirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PAVGWirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PCMPEQBirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PCMPEQDirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PCMPEQWirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PCMPGTBirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PCMPGTDirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PCMPGTWirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PMAXSWirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PMAXUBirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PMINSWirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PMINUBirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSIGNBrm64")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSIGNDrm64")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSIGNWrm64")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSUBBirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSUBDirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSUBQirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSUBSBirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSUBSWirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSUBUSBirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSUBUSWirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSUBWirm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "MOVBE64rm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PABSBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PABSDrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PABSWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PADDBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PADDDrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PADDQrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PADDSBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PADDSWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PADDUSBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PADDUSWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PADDWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PAVGBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PAVGWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PCMPEQBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PCMPEQDrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PCMPEQQrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PCMPEQWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PCMPGTBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PCMPGTDrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PCMPGTWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PMAXSBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PMAXSDrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PMAXSWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PMAXUBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PMAXUDrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PMAXUWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PMINSBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PMINSDrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PMINSWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PMINUBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PMINUDrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PMINUWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PSIGNBrm128")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PSIGNDrm128")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PSIGNWrm128")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PSUBBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PSUBDrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PSUBQrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PSUBSBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PSUBSWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PSUBUSBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PSUBUSWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "PSUBWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPABSBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPABSBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPABSDYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPABSDrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPABSWYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPABSWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPADDBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPADDBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPADDDrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPADDDrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPADDQYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPADDQrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPADDSBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPADDSBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPADDSWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPADDSWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPADDUSBYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPADDUSBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPADDUSWYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPADDUSWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPADDWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPADDWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPAVGBYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPAVGBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPAVGWYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPAVGWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPEQBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPEQBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPEQDrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPEQDrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPEQQrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPEQQrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPEQWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPEQWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPGTBYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPGTBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPGTDYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPGTDrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPGTWYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPGTWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPMAXSBYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPMAXSBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPMAXSDYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPMAXSDrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPMAXSWYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPMAXSWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPMAXUBYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPMAXUBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPMAXUDYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPMAXUDrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPMAXUWYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPMAXUWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPMINSBYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPMINSBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPMINSDYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPMINSDrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPMINSWYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPMINSWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPMINUBYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPMINUBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPMINUDYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPMINUDrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPMINUWYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPMINUWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPSIGNBYrm256")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPSIGNBrm128")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPSIGNDYrm256")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPSIGNDrm128")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPSIGNWYrm256")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPSIGNWrm128")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBBYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBDYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBDrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBQYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBQrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBSBYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBSBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBSWYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBSWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBUSBYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBUSBrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBUSWYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBUSWrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBWYrm")>;
> +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBWrm")>;
>
> -def WriteP1_P5_Lat6Ld : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> {
> - let Latency = 10;
> - let NumMicroOps = 3;
> - let ResourceCycles = [1, 1, 1];
> +def HWWriteResGroup16 : SchedWriteRes<[HWPort23,HWPort015]> {
> + let Latency = 1;
> + let NumMicroOps = 2;
> + let ResourceCycles = [1,1];
> }
> +def: InstRW<[HWWriteResGroup16], (instregex "BLENDPDrmi")>;
> +def: InstRW<[HWWriteResGroup16], (instregex "BLENDPSrmi")>;
> +def: InstRW<[HWWriteResGroup16], (instregex "MMX_PANDNirm")>;
> +def: InstRW<[HWWriteResGroup16], (instregex "MMX_PANDirm")>;
> +def: InstRW<[HWWriteResGroup16], (instregex "MMX_PORirm")>;
> +def: InstRW<[HWWriteResGroup16], (instregex "MMX_PXORirm")>;
> +def: InstRW<[HWWriteResGroup16], (instregex "PANDNrm")>;
> +def: InstRW<[HWWriteResGroup16], (instregex "PANDrm")>;
> +def: InstRW<[HWWriteResGroup16], (instregex "PORrm")>;
> +def: InstRW<[HWWriteResGroup16], (instregex "PXORrm")>;
> +def: InstRW<[HWWriteResGroup16], (instregex "VBLENDPDYrmi")>;
> +def: InstRW<[HWWriteResGroup16], (instregex "VBLENDPDrmi")>;
> +def: InstRW<[HWWriteResGroup16], (instregex "VBLENDPSYrmi")>;
> +def: InstRW<[HWWriteResGroup16], (instregex "VBLENDPSrmi")>;
> +def: InstRW<[HWWriteResGroup16], (instregex "VINSERTF128rm")>;
> +def: InstRW<[HWWriteResGroup16], (instregex "VINSERTI128rm")>;
> +def: InstRW<[HWWriteResGroup16], (instregex "VPANDNYrm")>;
> +def: InstRW<[HWWriteResGroup16], (instregex "VPANDNrm")>;
> +def: InstRW<[HWWriteResGroup16], (instregex "VPANDYrm")>;
> +def: InstRW<[HWWriteResGroup16], (instregex "VPANDrm")>;
> +def: InstRW<[HWWriteResGroup16], (instregex "VPBLENDDYrmi")>;
> +def: InstRW<[HWWriteResGroup16], (instregex "VPBLENDDrmi")>;
> +def: InstRW<[HWWriteResGroup16], (instregex "VPORYrm")>;
> +def: InstRW<[HWWriteResGroup16], (instregex "VPORrm")>;
> +def: InstRW<[HWWriteResGroup16], (instregex "VPXORYrm")>;
> +def: InstRW<[HWWriteResGroup16], (instregex "VPXORrm")>;
>
> -// Starting with P2.
> -def Write2P237_P4 : SchedWriteRes<[HWPort237, HWPort4]> {
> +def HWWriteResGroup17 : SchedWriteRes<[HWPort23,HWPort0156]> {
> let Latency = 1;
> - let ResourceCycles = [2, 1];
> + let NumMicroOps = 2;
> + let ResourceCycles = [1,1];
> }
> +def: InstRW<[HWWriteResGroup17], (instregex "ADD64rm")>;
> +def: InstRW<[HWWriteResGroup17], (instregex "ADD8rm")>;
> +def: InstRW<[HWWriteResGroup17], (instregex "AND64rm")>;
> +def: InstRW<[HWWriteResGroup17], (instregex "AND8rm")>;
> +def: InstRW<[HWWriteResGroup17], (instregex "CMP64mi8")>;
> +def: InstRW<[HWWriteResGroup17], (instregex "CMP64mr")>;
> +def: InstRW<[HWWriteResGroup17], (instregex "CMP64rm")>;
> +def: InstRW<[HWWriteResGroup17], (instregex "CMP8mi")>;
> +def: InstRW<[HWWriteResGroup17], (instregex "CMP8mr")>;
> +def: InstRW<[HWWriteResGroup17], (instregex "CMP8rm")>;
> +def: InstRW<[HWWriteResGroup17], (instregex "OR64rm")>;
> +def: InstRW<[HWWriteResGroup17], (instregex "OR8rm")>;
> +def: InstRW<[HWWriteResGroup17], (instregex "POP64r")>;
> +def: InstRW<[HWWriteResGroup17], (instregex "SUB64rm")>;
> +def: InstRW<[HWWriteResGroup17], (instregex "SUB8rm")>;
> +def: InstRW<[HWWriteResGroup17], (instregex "TEST64rm")>;
> +def: InstRW<[HWWriteResGroup17], (instregex "TEST8mi")>;
> +def: InstRW<[HWWriteResGroup17], (instregex "TEST8rm")>;
> +def: InstRW<[HWWriteResG
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