
<div dir="ltr">This commit cites a Phabricator revision that never actually went to 'llvm-commits' for review. Further, that revision never got a final LGTM and I pointed out several issues with this commit on Phabricator before realizing it wasn't even going to the full list. Here is the response I sent to Phab:<div><br></div><div>----</div><div><div>While the work here is pretty great, you were asked to wait for someone else to LGTM and you didn't. That's really poor form. There are plenty of issues here that really should be addressed before this was landed. Please revert and start looking at them.</div><div><br></div><div>1) The commit message is very poorly formated and doesn't actually describe the kinds of differences that people should expect.</div><div>2) There are *numerous* substantial changes to the tests that are completely unrelated to this patch. For example, see the 'half.ll' test case. Please update the FileCheck lines for tests you need to modify in a NFC patch that *just* gives you a clean baseline so that the only thing changing here are the scheduling differences. this is especially important considering how many tests are changed and in how many ways.</div><div>3) This gives a very significant new influx of data to the scheduler. I'm actually really excited about that. However, even looking at thet test cases updated, I see substantially different instruction sequences. What testing have you done to ensure this is correct? We have at least one internal user (based on Halide) that sees correctness regressions after this commit. It may not be this commit that has the bug, but if we have latent missing constraints on instructions (which we probably do) massive changes to the scheduler are likely to expose bugs. It may be worth discussing in the change what testing has been done and ask others to help test such a large change as this.</div><div><br></div><div>Thanks,</div><div>-Chandler</div></div><div>----</div><div><br></div><div>Given that the review didn't even happen on the list, and that we have some indications that this *is* uncovering some latent issues in the x86 backend (missing constraints that now show up due to scheduler changes likely?) I've asked folks to go ahead and revert this until it gets sorted out.</div><div><br></div><div>-Chandler</div></div><br><div class="gmail_quote"><div dir="ltr">On Tue, Jun 27, 2017 at 8:05 AM Gadi Haber via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: gadi.haber<br>

Date: Tue Jun 27 08:05:13 2017<br>

New Revision: 306414<br>

<br>

URL: <a href="http://llvm.org/viewvc/llvm-project?rev=306414&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=306414&view=rev</a><br>

Log:<br>

Updated and extended the information about each instruction in HSW and SNB to include the following data:<br>

•static latency<br>

•number of uOps from which the instructions consists<br>

•all ports used by the instruction<br>

<br>

Reviewers: <br>

 RKSimon<br>

 zvi<br>

aymanmus<br>

m_zuckerman<br>

<br>

Differential Revision: <a href="https://reviews.llvm.org/D33897" rel="noreferrer" target="_blank">https://reviews.llvm.org/D33897</a><br>

<br>

<br>

Modified:<br>

    llvm/trunk/lib/Target/X86/X86SchedHaswell.td<br>

    llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td<br>

    llvm/trunk/test/CodeGen/X86/avx-schedule.ll<br>

    llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll<br>

    llvm/trunk/test/CodeGen/X86/avx2-schedule.ll<br>

    llvm/trunk/test/CodeGen/X86/avx2-vector-shifts.ll<br>

    llvm/trunk/test/CodeGen/X86/avx512-cmp.ll<br>

    llvm/trunk/test/CodeGen/X86/avx512-cvt.ll<br>

    llvm/trunk/test/CodeGen/X86/avx512-insert-extract.ll<br>

    llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.ll<br>

    llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll<br>

    llvm/trunk/test/CodeGen/X86/avx512-vec-cmp.ll<br>

    llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll<br>

    llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll<br>

    llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-256.ll<br>

    llvm/trunk/test/CodeGen/X86/extractelement-legalization-store-ordering.ll<br>

    llvm/trunk/test/CodeGen/X86/fp128-i128.ll<br>

    llvm/trunk/test/CodeGen/X86/gather-addresses.ll<br>

    llvm/trunk/test/CodeGen/X86/half.ll<br>

    llvm/trunk/test/CodeGen/X86/illegal-bitfield-loadstore.ll<br>

    llvm/trunk/test/CodeGen/X86/mul-constant-i32.ll<br>

    llvm/trunk/test/CodeGen/X86/mul-constant-i64.ll<br>

    llvm/trunk/test/CodeGen/X86/pr32329.ll<br>

    llvm/trunk/test/CodeGen/X86/recip-fastmath.ll<br>

    llvm/trunk/test/CodeGen/X86/recip-fastmath2.ll<br>

    llvm/trunk/test/CodeGen/X86/sse-schedule.ll<br>

    llvm/trunk/test/CodeGen/X86/sse2-schedule.ll<br>

    llvm/trunk/test/CodeGen/X86/sse3-schedule.ll<br>

    llvm/trunk/test/CodeGen/X86/sse41-schedule.ll<br>

    llvm/trunk/test/CodeGen/X86/sse42-schedule.ll<br>

    llvm/trunk/test/CodeGen/X86/ssse3-schedule.ll<br>

    llvm/trunk/test/CodeGen/X86/vector-shift-ashr-512.ll<br>

    llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v32.ll<br>

<br>

Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td<br>

URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=306414&r1=306413&r2=306414&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=306414&r1=306413&r2=306414&view=diff</a><br>

==============================================================================<br>

--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)<br>

+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Tue Jun 27 08:05:13 2017<br>

@@ -23,8 +23,8 @@ def HaswellModel : SchedMachineModel {<br>

   // Based on the LSD (loop-stream detector) queue size and benchmarking data.<br>

   let LoopMicroOpBufferSize = 50;<br>

<br>

-  // FIXME: SSE4 and AVX are unimplemented. This flag is set to allow<br>

-  // the scheduler to assign a default model to unrecognized opcodes.<br>

+  // This flag is set to allow the scheduler to assign a default model to<br>

+  // unrecognized opcodes.<br>

   let CompleteModel = 0;<br>

 }<br>

<br>

@@ -267,1914 +267,3251 @@ def : WriteRes<WriteMicrocoded, [HWPort0<br>

 def : WriteRes<WriteFence,  [HWPort23, HWPort4]>;<br>

 def : WriteRes<WriteNop, []>;<br>

<br>

-//================ Exceptions ================//<br>

-<br>

-//-- Specific Scheduling Models --//<br>

-<br>

-// Starting with P0.<br>

-def WriteP0 : SchedWriteRes<[HWPort0]>;<br>

-<br>

-def WriteP0_P1_Lat4 : SchedWriteRes<[HWPort0, HWPort1]> {<br>

-  let Latency = 4;<br>

-  let NumMicroOps = 2;<br>

-  let ResourceCycles = [1, 1];<br>

-}<br>

+////////////////////////////////////////////////////////////////////////////////<br>

+// Horizontal add/sub  instructions.<br>

+////////////////////////////////////////////////////////////////////////////////<br>

<br>

-def WriteP0_P1_Lat4Ld : SchedWriteRes<[HWPort0, HWPort1, HWPort23]> {<br>

-  let Latency = 8;<br>

+// HADD, HSUB PS/PD<br>

+// x,x / v,v,v.<br>

+def : WriteRes<WriteFHAdd, [HWPort1, HWPort5]> {<br>

+  let Latency = 5;<br>

   let NumMicroOps = 3;<br>

-  let ResourceCycles = [1, 1, 1];<br>

+  let ResourceCycles = [1, 2];<br>

 }<br>

<br>

-def WriteP01 : SchedWriteRes<[HWPort01]>;<br>

+// x,m / v,v,m.<br>

+def : WriteRes<WriteFHAddLd, [HWPort1, HWPort5, HWPort23]> {<br>

+  let Latency = 9;<br>

+  let NumMicroOps = 4;<br>

+  let ResourceCycles = [1, 2, 1];<br>

+}<br>

<br>

-def Write2P01 : SchedWriteRes<[HWPort01]> {<br>

-  let NumMicroOps = 2;<br>

+// PHADD|PHSUB (S) W/D.<br>

+// v <- v,v.<br>

+def : WriteRes<WritePHAdd, [HWPort1, HWPort5]> {<br>

+  let Latency = 3;<br>

+  let NumMicroOps = 3;<br>

+  let ResourceCycles = [1, 2];<br>

 }<br>

-def Write3P01 : SchedWriteRes<[HWPort01]> {<br>

+// v <- v,m.<br>

+def : WriteRes<WritePHAddLd, [HWPort1, HWPort5, HWPort23]> {<br>

+  let Latency = 6;<br>

   let NumMicroOps = 3;<br>

+  let ResourceCycles = [1, 2, 1];<br>

 }<br>

<br>

-def WriteP015 : SchedWriteRes<[HWPort015]>;<br>

+// Remaining instrs.<br>

<br>

-def WriteP01_P5 : SchedWriteRes<[HWPort01, HWPort5]> {<br>

-  let NumMicroOps = 2;<br>

+def HWWriteResGroup0 : SchedWriteRes<[HWPort23]> {<br>

+  let Latency = 0;<br>

+  let NumMicroOps = 1;<br>

+  let ResourceCycles = [1];<br>

 }<br>

-def WriteP06 : SchedWriteRes<[HWPort06]>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "LDDQUrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "MMX_MOVD64from64rm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "MMX_MOVD64rm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "MMX_MOVD64to64rm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "MMX_MOVQ64rm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "MOV32rm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "MOV64toPQIrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "MOV8rm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "MOVAPDrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "MOVAPSrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "MOVDDUPrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "MOVDI2PDIrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "MOVDQArm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "MOVDQUrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "MOVNTDQArm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "MOVSHDUPrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "MOVSLDUPrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "MOVSSrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "MOVSX32rm16")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "MOVSX32rm8")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "MOVUPDrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "MOVUPSrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "MOVZX32rm16")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "MOVZX32rm8")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "PREFETCHNTA")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "PREFETCHT0")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "PREFETCHT1")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "PREFETCHT2")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VBROADCASTF128")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VBROADCASTI128")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VBROADCASTSDYrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VBROADCASTSSrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VBROADCASTSSrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VLDDQUYrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VLDDQUrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VMOV64toPQIrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VMOVAPDYrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VMOVAPDrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VMOVAPSYrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VMOVAPSrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VMOVDDUPYrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VMOVDDUPrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VMOVDI2PDIrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VMOVDQAYrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VMOVDQArm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VMOVDQUYrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VMOVDQUrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VMOVNTDQAYrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VMOVNTDQArm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VMOVQI2PQIrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VMOVSDrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VMOVSHDUPYrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VMOVSHDUPrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VMOVSLDUPYrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VMOVSLDUPrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VMOVSSrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VMOVUPDYrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VMOVUPDrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VMOVUPSYrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VMOVUPSrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VPBROADCASTDYrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VPBROADCASTDrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VPBROADCASTQYrm")>;<br>

+def: InstRW<[HWWriteResGroup0], (instregex "VPBROADCASTQrm")>;<br>

+<br>

+def HWWriteResGroup1 : SchedWriteRes<[HWPort4,HWPort237]> {<br>

+  let Latency = 0;<br>

+  let NumMicroOps = 2;<br>

+  let ResourceCycles = [1,1];<br>

+}<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MMX_MOVD64from64rm")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MMX_MOVD64mr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MMX_MOVNTQmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MMX_MOVQ64mr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MOV64mr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MOV8mi")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MOV8mr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MOVAPDmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MOVAPSmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MOVDQAmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MOVDQUmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MOVHPDmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MOVHPSmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MOVLPDmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MOVLPSmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MOVNTDQmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MOVNTI_64mr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MOVNTImr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MOVNTPDmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MOVNTPSmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MOVPDI2DImr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MOVPQI2QImr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MOVPQIto64mr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MOVSSmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MOVUPDmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "MOVUPSmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VEXTRACTF128mr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VEXTRACTI128mr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVAPDYmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVAPDmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVAPSYmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVAPSmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVDQAYmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVDQAmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVDQUYmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVDQUmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVHPDmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVHPSmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVLPDmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVLPSmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTDQYmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTDQmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTPDYmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTPDmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTPSYmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTPSmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVPDI2DImr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVPQI2QImr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVPQIto64mr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVSDmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVSSmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVUPDYmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVUPDmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVUPSYmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMOVUPSmr")>;<br>

+def: InstRW<[HWWriteResGroup1], (instregex "VMPTRSTm")>;<br>

<br>

-def Write2P06 : SchedWriteRes<[HWPort06]> {<br>

+def HWWriteResGroup2 : SchedWriteRes<[HWPort0]> {<br>

   let Latency = 1;<br>

-  let NumMicroOps = 2;<br>

-  let ResourceCycles = [2];<br>

+  let NumMicroOps = 1;<br>

+  let ResourceCycles = [1];<br>

 }<br>

+def: InstRW<[HWWriteResGroup2], (instregex "MMX_MOVD64from64rr")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "MMX_MOVD64grr")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "MMX_PMOVMSKBrr")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLDri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLDrr")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLQri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLQrr")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLWri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLWrr")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRADri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRADrr")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRAWri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRAWrr")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLDri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLDrr")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLQri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLQrr")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLWri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLWrr")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "MOVPDI2DIrr")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "MOVPQIto64rr")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "PSLLDri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "PSLLQri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "PSLLWri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "PSRADri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "PSRAWri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "PSRLDri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "PSRLQri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "PSRLWri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VMOVPDI2DIrr")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VMOVPQIto64rr")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VPSLLDri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VPSLLDrm")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VPSLLQri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VPSLLQrm")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VPSLLVQYrr")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VPSLLVQrr")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VPSLLWri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VPSLLWrm")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VPSRADYri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VPSRADri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VPSRAWYri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VPSRAWri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VPSRLDYri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VPSRLDri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VPSRLQYri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VPSRLQri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VPSRLVQYrr")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VPSRLVQrr")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VPSRLWYri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VPSRLWri")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VTESTPDYrr")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VTESTPDrr")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VTESTPSYrr")>;<br>

+def: InstRW<[HWWriteResGroup2], (instregex "VTESTPSrr")>;<br>

<br>

-def Write3P06_Lat2 : SchedWriteRes<[HWPort06]> {<br>

-  let Latency = 2;<br>

-  let NumMicroOps = 3;<br>

-  let ResourceCycles = [3];<br>

+def HWWriteResGroup3 : SchedWriteRes<[HWPort1]> {<br>

+  let Latency = 1;<br>

+  let NumMicroOps = 1;<br>

+  let ResourceCycles = [1];<br>

 }<br>

+def: InstRW<[HWWriteResGroup3], (instregex "MASKMOVDQU64")>;<br>

+def: InstRW<[HWWriteResGroup3], (instregex "MMX_MASKMOVQ64")>;<br>

<br>

-def WriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {<br>

-  let NumMicroOps = 2;<br>

+def HWWriteResGroup4 : SchedWriteRes<[HWPort5]> {<br>

+  let Latency = 1;<br>

+  let NumMicroOps = 1;<br>

+  let ResourceCycles = [1];<br>

 }<br>

+def: InstRW<[HWWriteResGroup4], (instregex "ANDNPDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "ANDNPSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "ANDPDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "ANDPSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "INSERTPSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "KORTESTBrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVD64rr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVD64to64rr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVQ2DQrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "MMX_PALIGNR64irr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "MMX_PSHUFBrr64")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "MMX_PSHUFWri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKHBWirr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKHDQirr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKHWDirr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKLBWirr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKLDQirr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKLWDirr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "MOV64toPQIrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "MOVAPDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "MOVAPSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "MOVDDUPrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "MOVDI2PDIrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "MOVHLPSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "MOVLHPSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "MOVSDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "MOVSHDUPrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "MOVSLDUPrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "MOVSSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "MOVUPDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "MOVUPSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "ORPDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "ORPSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PACKSSDWrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PACKSSWBrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PACKUSDWrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PACKUSWBrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PALIGNRrri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PBLENDWrri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXBDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXBQrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXBWrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXDQrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXWDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXWQrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXBDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXBQrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXBWrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXDQrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXWDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXWQrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PSHUFBrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PSHUFDri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PSHUFHWri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PSHUFLWri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PSLLDQri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PSRLDQri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKHBWrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKHDQrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKHQDQrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKHWDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKLBWrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKLDQrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKLQDQrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKLWDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "SHUFPDrri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "SHUFPSrri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "UNPCKHPDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "UNPCKHPSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "UNPCKLPDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "UNPCKLPSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VANDNPDYrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VANDNPDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VANDNPSYrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VANDNPSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VANDPDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VANDPDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VANDPSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VBROADCASTSSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VGATHERQPSZrm")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VINSERTPSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VMOV64toPQIrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VMOV64toPQIrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPDYrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPSYrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VMOVDDUPYrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VMOVDDUPrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VMOVHLPSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VMOVLHPSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VMOVSDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VMOVSHDUPYrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VMOVSHDUPrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VMOVSLDUPYrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VMOVSLDUPrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VMOVSSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPDYrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPSYrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VORPDYrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VORPDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VORPSYrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VORPSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPACKSSDWYrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPACKSSDWrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPACKSSWBYrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPACKSSWBrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPACKUSDWYrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPACKUSDWrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPACKUSWBYrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPACKUSWBrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPALIGNRYrri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPALIGNRrri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPBLENDWYrri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPBLENDWrri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPBROADCASTDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPBROADCASTQrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPDri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPDrm")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPSri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPSrm")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXBDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXBQrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXBWrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXDQrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXWDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXWQrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXBDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXBQrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXBWrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXDQrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXWDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXWQrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFBrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFBrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFDYri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFDri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFHWri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFLWYri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFLWri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPSLLDQYri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPSLLDQri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPSRLDQYri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPSRLDQri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHBWYrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHBWrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHDQYrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHDQrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHQDQrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHWDYrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHWDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLBWrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLDQYrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLDQrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLQDQYrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLQDQrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLWDYrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLWDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VSHUFPDYrri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VSHUFPDrri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VSHUFPSYrri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VSHUFPSrri")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKHPDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKHPSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKLPDYrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKLPDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKLPSYrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKLPSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VXORPDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "VXORPSrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "XORPDrr")>;<br>

+def: InstRW<[HWWriteResGroup4], (instregex "XORPSrr")>;<br>

<br>

-def Write2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {<br>

-  let NumMicroOps = 3;<br>

-  let ResourceCycles = [2, 1];<br>

+def HWWriteResGroup5 : SchedWriteRes<[HWPort6]> {<br>

+  let Latency = 1;<br>

+  let NumMicroOps = 1;<br>

+  let ResourceCycles = [1];<br>

 }<br>

+def: InstRW<[HWWriteResGroup5], (instregex "JMP64r")>;<br>

<br>

-def Write2P0156_Lat2 : SchedWriteRes<[HWPort0156]> {<br>

-  let Latency = 2;<br>

-  let ResourceCycles = [2];<br>

-}<br>

-def Write2P0156_Lat2Ld : SchedWriteRes<[HWPort0156, HWPort23]> {<br>

-  let Latency = 6;<br>

-  let ResourceCycles = [2, 1];<br>

+def HWWriteResGroup6 : SchedWriteRes<[HWPort01]> {<br>

+  let Latency = 1;<br>

+  let NumMicroOps = 1;<br>

+  let ResourceCycles = [1];<br>

 }<br>

+def: InstRW<[HWWriteResGroup6], (instregex "FINCSTP")>;<br>

+def: InstRW<[HWWriteResGroup6], (instregex "FNOP")>;<br>

<br>

-def Write5P0156 : SchedWriteRes<[HWPort0156]> {<br>

-  let NumMicroOps = 5;<br>

-  let ResourceCycles = [5];<br>

+def HWWriteResGroup7 : SchedWriteRes<[HWPort0]> {<br>

+  let Latency = 1;<br>

+  let NumMicroOps = 1;<br>

+  let ResourceCycles = [1];<br>

 }<br>

+def: InstRW<[HWWriteResGroup7], (instregex "BT32ri8")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "BT32rr")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "BTC32ri8")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "BTC32rr")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "BTR32ri8")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "BTR32rr")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "BTS32ri8")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "BTS32rr")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "CDQ")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "CQO")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "RORX32ri")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "RORX64ri")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SAR32ri")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SAR64r1")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SAR8r1")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SAR8ri")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SARX32rr")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SARX64rr")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SETAEr")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SETBr")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SETEr")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SETGEr")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SETGr")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SETLEr")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SETLr")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SETNEr")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SETNOr")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SETNPr")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SETNSr")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SETOr")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SETPr")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SETSr")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SHL32ri")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SHL64r1")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SHL8r1")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SHL8ri")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SHLX32rr")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SHLX64rr")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SHR32ri")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SHR64r1")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SHR8r1")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SHR8ri")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SHRX32rr")>;<br>

+def: InstRW<[HWWriteResGroup7], (instregex "SHRX64rr")>;<br>

<br>

-def WriteP0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {<br>

+def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> {<br>

   let Latency = 1;<br>

-  let ResourceCycles = [1, 2, 1];<br>

+  let NumMicroOps = 1;<br>

+  let ResourceCycles = [1];<br>

 }<br>

+def: InstRW<[HWWriteResGroup8], (instregex "ANDN32rr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "ANDN64rr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "BLSI32rr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "BLSI64rr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "BLSMSK32rr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "BLSMSK64rr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "BLSR32rr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "BLSR64rr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "BZHI32rr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "BZHI64rr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "LEA64_32r")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSBrr64")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSDrr64")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSWrr64")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDBirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDDirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDQirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDSBirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDSWirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDUSBirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDUSWirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDWirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PAVGBirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PAVGWirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPEQBirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPEQDirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPEQWirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPGTBirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPGTDirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPGTWirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PMAXSWirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PMAXUBirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PMINSWirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PMINUBirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSIGNBrr64")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSIGNDrr64")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSIGNWrr64")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBBirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBDirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBQirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBSBirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBSWirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBUSBirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBUSWirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBWirr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PABSBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PABSDrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PABSWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PADDBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PADDDrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PADDQrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PADDSBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PADDSWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PADDUSBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PADDUSWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PADDWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PAVGBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PAVGWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PCMPEQBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PCMPEQDrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PCMPEQQrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PCMPEQWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PCMPGTBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PCMPGTDrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PCMPGTWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PMAXSBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PMAXSDrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PMAXSWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PMAXUBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PMAXUDrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PMAXUWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PMINSBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PMINSDrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PMINSWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PMINUBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PMINUDrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PMINUWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PSIGNBrr128")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PSIGNDrr128")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PSIGNWrr128")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PSUBBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PSUBDrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PSUBQrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PSUBSBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PSUBSWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PSUBUSBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PSUBUSWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "PSUBWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VMASKMOVPSYrm")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPABSBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPABSBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPABSDYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPABSDrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPABSWYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPABSWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPADDBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPADDBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPADDDrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPADDDrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPADDQYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPADDQrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPADDSBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPADDSWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPADDUSBYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPADDUSBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPADDUSWYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPADDUSWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPADDWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPAVGBYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPAVGBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPAVGWYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPAVGWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQDrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQDrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQQrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTBYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTDYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTDrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTWYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSBYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSDYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSDrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSWYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUBYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUDYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUDrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUWYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPMINSBYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPMINSBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPMINSDYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPMINSDrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPMINSWYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPMINSWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPMINUBYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPMINUBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPMINUDYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPMINUDrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPMINUWYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPMINUWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNBYrr256")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNBrr128")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNDYrr256")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNDrr128")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNWYrr256")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNWrr128")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPSUBBYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPSUBBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPSUBDYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPSUBDrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPSUBQYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPSUBQrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPSUBSBYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPSUBSBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPSUBSWYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPSUBSWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPSUBUSBYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPSUBUSBrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPSUBUSWYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPSUBUSWrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPSUBWYrr")>;<br>

+def: InstRW<[HWWriteResGroup8], (instregex "VPSUBWrr")>;<br>

<br>

-def Write2P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {<br>

+def HWWriteResGroup9 : SchedWriteRes<[HWPort015]> {<br>

   let Latency = 1;<br>

-  let ResourceCycles = [2, 2, 1];<br>

+  let NumMicroOps = 1;<br>

+  let ResourceCycles = [1];<br>

 }<br>

+def: InstRW<[HWWriteResGroup9], (instregex "BLENDPDrri")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "BLENDPSrri")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "MMX_MOVD64from64rr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "MMX_MOVQ64rr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "MMX_PANDNirr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "MMX_PANDirr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "MMX_PORirr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "MMX_PXORirr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "MOVDQArr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "MOVDQUrr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "MOVPQI2QIrr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "PANDNrr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "PANDrr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "PORrr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "PXORrr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "VBLENDPDYrri")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "VBLENDPDrri")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "VBLENDPSYrri")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "VBLENDPSrri")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQAYrr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQArr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQUYrr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQUrr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "VMOVPQI2QIrr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "VMOVZPQILo2PQIrr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "VPANDNYrr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "VPANDNrr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "VPANDYrr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "VPANDrr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "VPBLENDDYrri")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "VPBLENDDrri")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "VPORYrr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "VPORrr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "VPXORYrr")>;<br>

+def: InstRW<[HWWriteResGroup9], (instregex "VPXORrr")>;<br>

<br>

-def Write3P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {<br>

+def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> {<br>

   let Latency = 1;<br>

-  let ResourceCycles = [3, 2, 1];<br>

+  let NumMicroOps = 1;<br>

+  let ResourceCycles = [1];<br>

 }<br>

+def: InstRW<[HWWriteResGroup10], (instregex "ADD32ri8")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "ADD32rr")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "ADD8ri")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "ADD8rr")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "AND32ri")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "AND64ri8")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "AND64rr")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "AND8ri")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "AND8rr")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "CBW")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "CLC")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "CMC")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "CMP16ri8")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "CMP32i32")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "CMP64rr")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "CMP8ri")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "CMP8rr")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "CWDE")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "DEC64r")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "DEC8r")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "INC64r")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "INC8r")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "LAHF")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "MOV32rr")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "MOV8ri")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "MOV8rr")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "MOVSX32rr16")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "MOVSX32rr8")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "MOVZX32rr16")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "MOVZX32rr8")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "NEG64r")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "NEG8r")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "NOOP")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "NOT64r")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "NOT8r")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "OR64ri8")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "OR64rr")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "OR8ri")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "OR8rr")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "SAHF")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "SGDT64m")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "SIDT64m")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "SLDT16m")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "SMSW16m")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "STC")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "STRm")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "SUB64ri8")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "SUB64rr")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "SUB8ri")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "SUB8rr")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "SYSCALL")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "TEST64rr")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "TEST8ri")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "TEST8rr")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "XCHG64rr")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "XOR32rr")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "XOR64ri8")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "XOR8ri")>;<br>

+def: InstRW<[HWWriteResGroup10], (instregex "XOR8rr")>;<br>

<br>

-// Starting with P1.<br>

-def WriteP1 : SchedWriteRes<[HWPort1]>;<br>

-<br>

-def WriteP1_P23 : SchedWriteRes<[HWPort1, HWPort23]> {<br>

+def HWWriteResGroup11 : SchedWriteRes<[HWPort0,HWPort23]> {<br>

+  let Latency = 1;<br>

   let NumMicroOps = 2;<br>

+  let ResourceCycles = [1,1];<br>

 }<br>

-def WriteP1_Lat3 : SchedWriteRes<[HWPort1]> {<br>

-  let Latency = 3;<br>

-}<br>

-def WriteP1_Lat3Ld : SchedWriteRes<[HWPort1, HWPort23]> {<br>

-  let Latency = 7;<br>

-}<br>

+def: InstRW<[HWWriteResGroup11], (instregex "CVTPS2PDrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "CVTSS2SDrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSLLDrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSLLQrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSLLWrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSRADrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSRAWrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSRLDrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSRLQrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSRLWrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "VCVTPH2PSYrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "VCVTPH2PSrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "VCVTPS2PDrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "VCVTSS2SDrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "VPSLLDYri")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "VPSLLQYri")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "VPSLLVQYrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "VPSLLVQrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "VPSLLWYri")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "VPSRADYrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "VPSRAWYrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "VPSRLDYrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "VPSRLQYrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "VPSRLVQYrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "VPSRLVQrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "VPSRLWYrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "VTESTPDYrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "VTESTPDrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "VTESTPSYrm")>;<br>

+def: InstRW<[HWWriteResGroup11], (instregex "VTESTPSrm")>;<br>

<br>

-def Write2P1 : SchedWriteRes<[HWPort1]> {<br>

+def HWWriteResGroup12 : SchedWriteRes<[HWPort5,HWPort23]> {<br>

+  let Latency = 1;<br>

   let NumMicroOps = 2;<br>

-  let ResourceCycles = [2];<br>

-}<br>

-def Write2P1_P23 : SchedWriteRes<[HWPort1, HWPort23]> {<br>

-  let NumMicroOps = 3;<br>

-  let ResourceCycles = [2, 1];<br>

-}<br>

-def WriteP15 : SchedWriteRes<[HWPort15]>;<br>

-def WriteP15Ld : SchedWriteRes<[HWPort15, HWPort23]> {<br>

-  let Latency = 4;<br>

+  let ResourceCycles = [1,1];<br>

 }<br>

+def: InstRW<[HWWriteResGroup12], (instregex "ANDNPDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "ANDNPSrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "ANDPDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "ANDPSrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "INSERTPSrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "MMX_PALIGNR64irm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "MMX_PINSRWirmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "MMX_PSHUFBrm64")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "MMX_PSHUFWmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "MMX_PUNPCKHBWirm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "MMX_PUNPCKHDQirm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "MMX_PUNPCKHWDirm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "MMX_PUNPCKLBWirm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "MMX_PUNPCKLDQirm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "MMX_PUNPCKLWDirm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "MOVHPDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "MOVHPSrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "MOVLPDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "MOVLPSrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "ORPDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "ORPSrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PACKSSDWrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PACKSSWBrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PACKUSDWrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PACKUSWBrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PALIGNRrmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PBLENDWrmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PINSRBrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PINSRDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PINSRQrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PINSRWrmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PMOVSXBDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PMOVSXBQrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PMOVSXBWrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PMOVSXDQrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PMOVSXWDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PMOVSXWQrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PMOVZXBDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PMOVZXBQrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PMOVZXBWrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PMOVZXDQrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PMOVZXWDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PMOVZXWQrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PSHUFBrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PSHUFDmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PSHUFHWmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PSHUFLWmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PUNPCKHBWrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PUNPCKHDQrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PUNPCKHQDQrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PUNPCKHWDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PUNPCKLBWrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PUNPCKLDQrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PUNPCKLQDQrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "PUNPCKLWDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "SHUFPDrmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "SHUFPSrmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "UNPCKHPDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "UNPCKHPSrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "UNPCKLPDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "UNPCKLPSrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VANDNPDYrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VANDNPDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VANDNPSYrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VANDNPSrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VANDPDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VANDPDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VANDPSrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VANDPSrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VINSERTPSrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VMOVHPDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VMOVHPSrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VMOVLPDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VMOVLPSrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VORPDYrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VORPDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VORPSYrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VORPSrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPACKSSDWYrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPACKSSDWrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPACKSSWBYrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPACKSSWBrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPACKUSDWYrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPACKUSDWrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPACKUSWBYrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPACKUSWBrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPALIGNRYrmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPALIGNRrmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPBLENDWYrmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPBLENDWrmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPERMILPDYri")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPERMILPDmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPERMILPDmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPERMILPDri")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPERMILPSYri")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPERMILPSmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPERMILPSmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPERMILPSri")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPINSRBrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPINSRDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPINSRQrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPINSRWrmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPMOVSXBDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPMOVSXBQrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPMOVSXBWrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPMOVSXDQrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPMOVSXWDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPMOVSXWQrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPMOVZXBDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPMOVZXBQrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPMOVZXBWrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPMOVZXDQrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPMOVZXWDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPMOVZXWQrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPSHUFBrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPSHUFBrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPSHUFDYmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPSHUFDmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPSHUFHWmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPSHUFHWmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPSHUFLWYmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPSHUFLWmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKHBWYrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKHBWrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKHDQYrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKHDQrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKHQDQrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKHQDQrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKHWDYrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKHWDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKLBWrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKLBWrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKLDQYrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKLDQrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKLQDQYrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKLQDQrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKLWDYrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKLWDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VSHUFPDYrmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VSHUFPDrmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VSHUFPSYrmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VSHUFPSrmi")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VUNPCKHPDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VUNPCKHPDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VUNPCKHPSrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VUNPCKHPSrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VUNPCKLPDYrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VUNPCKLPDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VUNPCKLPSYrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VUNPCKLPSrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VXORPDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VXORPDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VXORPSrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "VXORPSrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "XORPDrm")>;<br>

+def: InstRW<[HWWriteResGroup12], (instregex "XORPSrm")>;<br>

<br>

-def WriteP1_P5_Lat4 : SchedWriteRes<[HWPort1, HWPort5]> {<br>

-  let Latency = 4;<br>

+def HWWriteResGroup13 : SchedWriteRes<[HWPort6,HWPort23]> {<br>

+  let Latency = 1;<br>

   let NumMicroOps = 2;<br>

-  let ResourceCycles = [1, 1];<br>

+  let ResourceCycles = [1,1];<br>

 }<br>

+def: InstRW<[HWWriteResGroup13], (instregex "FARJMP64")>;<br>

+def: InstRW<[HWWriteResGroup13], (instregex "JMP64m")>;<br>

<br>

-def WriteP1_P5_Lat4Ld : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> {<br>

-  let Latency = 8;<br>

-  let NumMicroOps = 3;<br>

-  let ResourceCycles = [1, 1, 1];<br>

+def HWWriteResGroup14 : SchedWriteRes<[HWPort23,HWPort0]> {<br>

+  let Latency = 1;<br>

+  let NumMicroOps = 2;<br>

+  let ResourceCycles = [1,1];<br>

 }<br>

+def: InstRW<[HWWriteResGroup14], (instregex "BT64mi8")>;<br>

+def: InstRW<[HWWriteResGroup14], (instregex "RORX32mi")>;<br>

+def: InstRW<[HWWriteResGroup14], (instregex "RORX64mi")>;<br>

+def: InstRW<[HWWriteResGroup14], (instregex "SARX32rm")>;<br>

+def: InstRW<[HWWriteResGroup14], (instregex "SARX64rm")>;<br>

+def: InstRW<[HWWriteResGroup14], (instregex "SHLX32rm")>;<br>

+def: InstRW<[HWWriteResGroup14], (instregex "SHLX64rm")>;<br>

+def: InstRW<[HWWriteResGroup14], (instregex "SHRX32rm")>;<br>

+def: InstRW<[HWWriteResGroup14], (instregex "SHRX64rm")>;<br>

<br>

-def WriteP1_P5_Lat6 : SchedWriteRes<[HWPort1, HWPort5]> {<br>

-  let Latency = 6;<br>

+def HWWriteResGroup15 : SchedWriteRes<[HWPort23,HWPort15]> {<br>

+  let Latency = 1;<br>

   let NumMicroOps = 2;<br>

-  let ResourceCycles = [1, 1];<br>

+  let ResourceCycles = [1,1];<br>

 }<br>

+def: InstRW<[HWWriteResGroup15], (instregex "ANDN32rm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "ANDN64rm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "BLSI32rm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "BLSI64rm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "BLSMSK32rm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "BLSMSK64rm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "BLSR32rm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "BLSR64rm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "BZHI32rm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "BZHI64rm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PABSBrm64")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PABSDrm64")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PABSWrm64")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PADDBirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PADDDirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PADDQirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PADDSBirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PADDSWirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PADDUSBirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PADDUSWirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PADDWirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PAVGBirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PAVGWirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PCMPEQBirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PCMPEQDirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PCMPEQWirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PCMPGTBirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PCMPGTDirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PCMPGTWirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PMAXSWirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PMAXUBirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PMINSWirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PMINUBirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSIGNBrm64")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSIGNDrm64")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSIGNWrm64")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSUBBirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSUBDirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSUBQirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSUBSBirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSUBSWirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSUBUSBirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSUBUSWirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSUBWirm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "MOVBE64rm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PABSBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PABSDrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PABSWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PADDBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PADDDrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PADDQrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PADDSBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PADDSWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PADDUSBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PADDUSWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PADDWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PAVGBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PAVGWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PCMPEQBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PCMPEQDrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PCMPEQQrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PCMPEQWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PCMPGTBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PCMPGTDrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PCMPGTWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PMAXSBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PMAXSDrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PMAXSWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PMAXUBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PMAXUDrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PMAXUWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PMINSBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PMINSDrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PMINSWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PMINUBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PMINUDrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PMINUWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PSIGNBrm128")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PSIGNDrm128")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PSIGNWrm128")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PSUBBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PSUBDrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PSUBQrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PSUBSBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PSUBSWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PSUBUSBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PSUBUSWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "PSUBWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPABSBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPABSBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPABSDYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPABSDrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPABSWYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPABSWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPADDBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPADDBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPADDDrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPADDDrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPADDQYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPADDQrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPADDSBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPADDSBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPADDSWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPADDSWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPADDUSBYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPADDUSBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPADDUSWYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPADDUSWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPADDWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPADDWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPAVGBYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPAVGBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPAVGWYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPAVGWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPCMPEQBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPCMPEQBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPCMPEQDrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPCMPEQDrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPCMPEQQrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPCMPEQQrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPCMPEQWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPCMPEQWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPCMPGTBYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPCMPGTBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPCMPGTDYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPCMPGTDrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPCMPGTWYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPCMPGTWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPMAXSBYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPMAXSBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPMAXSDYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPMAXSDrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPMAXSWYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPMAXSWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPMAXUBYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPMAXUBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPMAXUDYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPMAXUDrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPMAXUWYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPMAXUWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPMINSBYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPMINSBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPMINSDYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPMINSDrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPMINSWYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPMINSWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPMINUBYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPMINUBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPMINUDYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPMINUDrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPMINUWYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPMINUWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPSIGNBYrm256")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPSIGNBrm128")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPSIGNDYrm256")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPSIGNDrm128")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPSIGNWYrm256")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPSIGNWrm128")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPSUBBYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPSUBBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPSUBDYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPSUBDrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPSUBQYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPSUBQrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPSUBSBYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPSUBSBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPSUBSWYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPSUBSWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPSUBUSBYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPSUBUSBrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPSUBUSWYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPSUBUSWrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPSUBWYrm")>;<br>

+def: InstRW<[HWWriteResGroup15], (instregex "VPSUBWrm")>;<br>

<br>

-def WriteP1_P5_Lat6Ld : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> {<br>

-  let Latency = 10;<br>

-  let NumMicroOps = 3;<br>

-  let ResourceCycles = [1, 1, 1];<br>

+def HWWriteResGroup16 : SchedWriteRes<[HWPort23,HWPort015]> {<br>

+  let Latency = 1;<br>

+  let NumMicroOps = 2;<br>

+  let ResourceCycles = [1,1];<br>

 }<br>

+def: InstRW<[HWWriteResGroup16], (instregex "BLENDPDrmi")>;<br>

+def: InstRW<[HWWriteResGroup16], (instregex "BLENDPSrmi")>;<br>

+def: InstRW<[HWWriteResGroup16], (instregex "MMX_PANDNirm")>;<br>

+def: InstRW<[HWWriteResGroup16], (instregex "MMX_PANDirm")>;<br>

+def: InstRW<[HWWriteResGroup16], (instregex "MMX_PORirm")>;<br>

+def: InstRW<[HWWriteResGroup16], (instregex "MMX_PXORirm")>;<br>

+def: InstRW<[HWWriteResGroup16], (instregex "PANDNrm")>;<br>

+def: InstRW<[HWWriteResGroup16], (instregex "PANDrm")>;<br>

+def: InstRW<[HWWriteResGroup16], (instregex "PORrm")>;<br>

+def: InstRW<[HWWriteResGroup16], (instregex "PXORrm")>;<br>

+def: InstRW<[HWWriteResGroup16], (instregex "VBLENDPDYrmi")>;<br>

+def: InstRW<[HWWriteResGroup16], (instregex "VBLENDPDrmi")>;<br>

+def: InstRW<[HWWriteResGroup16], (instregex "VBLENDPSYrmi")>;<br>

+def: InstRW<[HWWriteResGroup16], (instregex "VBLENDPSrmi")>;<br>

+def: InstRW<[HWWriteResGroup16], (instregex "VINSERTF128rm")>;<br>

+def: InstRW<[HWWriteResGroup16], (instregex "VINSERTI128rm")>;<br>

+def: InstRW<[HWWriteResGroup16], (instregex "VPANDNYrm")>;<br>

+def: InstRW<[HWWriteResGroup16], (instregex "VPANDNrm")>;<br>

+def: InstRW<[HWWriteResGroup16], (instregex "VPANDYrm")>;<br>

+def: InstRW<[HWWriteResGroup16], (instregex "VPANDrm")>;<br>

+def: InstRW<[HWWriteResGroup16], (instregex "VPBLENDDYrmi")>;<br>

+def: InstRW<[HWWriteResGroup16], (instregex "VPBLENDDrmi")>;<br>

+def: InstRW<[HWWriteResGroup16], (instregex "VPORYrm")>;<br>

+def: InstRW<[HWWriteResGroup16], (instregex "VPORrm")>;<br>

+def: InstRW<[HWWriteResGroup16], (instregex "VPXORYrm")>;<br>

+def: InstRW<[HWWriteResGroup16], (instregex "VPXORrm")>;<br>

<br>

-// Starting with P2.<br>

-def Write2P237_P4 : SchedWriteRes<[HWPort237, HWPort4]> {<br>

+def HWWriteResGroup17 : SchedWriteRes<[HWPort23,HWPort0156]> {<br>

   let Latency = 1;<br>

-  let ResourceCycles = [2, 1];<br>

+  let NumMicroOps = 2;<br>

+  let ResourceCycles = [1,1];<br>

 }<br>

+def: InstRW<[HWWriteResGroup17], (instregex "ADD64rm")>;<br>

+def: InstRW<[HWWriteResGroup17], (instregex "ADD8rm")>;<br>

+def: InstRW<[HWWriteResGroup17], (instregex "AND64rm")>;<br>

+def: InstRW<[HWWriteResGroup17], (instregex "AND8rm")>;<br>

+def: InstRW<[HWWriteResGroup17], (instregex "CMP64mi8")>;<br>

+def: InstRW<[HWWriteResGroup17], (instregex "CMP64mr")>;<br>

+def: InstRW<[HWWriteResGroup17], (instregex "CMP64rm")>;<br>

+def: InstRW<[HWWriteResGroup17], (instregex "CMP8mi")>;<br>

+def: InstRW<[HWWriteResGroup17], (instregex "CMP8mr")>;<br>

+def: InstRW<[HWWriteResGroup17], (instregex "CMP8rm")>;<br>

+def: InstRW<[HWWriteResGroup17], (instregex "OR64rm")>;<br>

+def: InstRW<[HWWriteResGroup17], (instregex "OR8rm")>;<br>

+def: InstRW<[HWWriteResGroup17], (instregex "POP64r")>;<br>

+def: InstRW<[HWWriteResGroup17], (instregex "SUB64rm")>;<br>

+def: InstRW<[HWWriteResGroup17], (instregex "SUB8rm")>;<br>

+def: InstRW<[HWWriteResGroup17], (instregex "TEST64rm")>;<br>

+def: InstRW<[HWWriteResGroup17], (instregex "TEST8mi")>;<br>

+def: InstRW<[HWWriteResGroup17], (instregex "TEST8rm")>;<br>

+def: InstRW<[HWWriteResG</blockquote></div>