Author: john.brawn
Date: Mon May 15 06:57:54 2017
New Revision: 303054
URL: http://llvm.org/viewvc/llvm-project?rev=303054&view=rev
Log:
[ARM] Mark LEApcrel instructions as isAsCheapAsAMove
Doing this means that if an LEApcrel is used in two places we will rematerialize
instead of generating two MOVs. This is particularly useful for printfs using
the same format string, where we want to generate an address into a register
that's going to get corrupted by the call.
Differential Revision: https://reviews.llvm.org/D32858
Added:
llvm/trunk/test/CodeGen/ARM/adr-remat.ll
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
llvm/trunk/test/CodeGen/ARM/align-sp-adjustment.ll
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=303054&r1=303053&r2=303054&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon May 15 06:57:54 2017
@@ -2222,7 +2222,7 @@ def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd),
let Inst{11-0} = label{11-0};
}
-let hasSideEffects = 0, isReMaterializable = 1 in
+let hasSideEffects = 0, isReMaterializable = 1, isAsCheapAsAMove = 1 in
def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=303054&r1=303053&r2=303054&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon May 15 06:57:54 2017
@@ -1402,7 +1402,7 @@ def tADR : T1I<(outs tGPR:$Rd), (ins t_a
let DecoderMethod = "DecodeThumbAddSpecialReg";
}
-let hasSideEffects = 0, isReMaterializable = 1 in
+let hasSideEffects = 0, isReMaterializable = 1, isAsCheapAsAMove = 1 in
def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
2, IIC_iALUi, []>, Sched<[WriteALU]>;
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=303054&r1=303053&r2=303054&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon May 15 06:57:54 2017
@@ -1227,7 +1227,7 @@ def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd
let DecoderMethod = "DecodeT2Adr";
}
-let hasSideEffects = 0, isReMaterializable = 1 in
+let hasSideEffects = 0, isReMaterializable = 1, isAsCheapAsAMove = 1 in
def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
let hasSideEffects = 1 in
Added: llvm/trunk/test/CodeGen/ARM/adr-remat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/adr-remat.ll?rev=303054&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/adr-remat.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/adr-remat.ll Mon May 15 06:57:54 2017
@@ -0,0 +1,25 @@
+; RUN: llc -mtriple=armv7a %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv7m %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv6m %s -o - | FileCheck %s
+
+ at str.1 = private unnamed_addr constant [58 x i8] c"+-------------------------------------------------------+\00"
+ at str.2 = private unnamed_addr constant [58 x i8] c"| |\00"
+
+declare i32 @puts(i8* nocapture readonly)
+
+; Check that we rematerialize the adr of str.1 instead of doing one adr and two
+; movs.
+
+; CHECK: adr r0, [[STR1:.LCPI[0-9]+_[0-9]+]]
+; CHECK: bl puts
+; CHECK: adr r0, {{.LCPI[0-9]+_[0-9]+}}
+; CHECK: bl puts
+; CHECK: adr r0, [[STR1]]
+; CHECK: b{{l?}} puts
+define void @fn() {
+entry:
+ %puts1 = tail call i32 @puts(i8* getelementptr inbounds ([58 x i8], [58 x i8]* @str.1, i32 0, i32 0))
+ %puts2 = tail call i32 @puts(i8* getelementptr inbounds ([58 x i8], [58 x i8]* @str.2, i32 0, i32 0))
+ %puts3 = tail call i32 @puts(i8* getelementptr inbounds ([58 x i8], [58 x i8]* @str.1, i32 0, i32 0))
+ ret void
+}
Modified: llvm/trunk/test/CodeGen/ARM/align-sp-adjustment.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/align-sp-adjustment.ll?rev=303054&r1=303053&r2=303054&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/align-sp-adjustment.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/align-sp-adjustment.ll Mon May 15 06:57:54 2017
@@ -1,6 +1,10 @@
; RUN: llc -mtriple=thumbv7 -o - %s | FileCheck %s
-; CHECK: [sp, #2120]
+; p5 will have been pushed to the stack. Check that it's correctly aligned by
+; looking at the offset of the instruction that loads it. Note that this is
+; very fragile and this test may need to be updated if we happen to spill more
+; or less to the stack.
+; CHECK: ldr{{(.w)?}} r{{[0-9]+}}, [sp, #2104]
%struct.struct_2 = type { [172 x %struct.struct_1] }
%struct.struct_1 = type { i32, i32, i32 }