[llvm] r303053 - [ARM] Mark LEApcrel as not having side effects

[John Brawn via llvm-commits]

Author: john.brawn
Date: Mon May 15 06:50:21 2017
New Revision: 303053

URL: http://llvm.org/viewvc/llvm-project?rev=303053&view=rev
Log:
[ARM] Mark LEApcrel as not having side effects

Doing this lets us hoist it out of loops, and I've also marked it as
rematerializable the same as the thumb1 and thumb2 counterparts.

It looks like it being marked as such was just a mistake, as the commit that
made that change only mentions LEApcrelJT and in thumb1 and thumb2 only the
LEApcrelJT instructions were marked as having side-effects, so it looks like
the intent was to only mark LEApcrelJT as having side-effects but LEApcrel was
accidentally marked as such also.

Differential Revision: https://reviews.llvm.org/D32857

Added:
    llvm/trunk/test/CodeGen/ARM/adr-hoist.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=303053&r1=303052&r2=303053&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon May 15 06:50:21 2017
@@ -2222,14 +2222,14 @@ def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd),
   let Inst{11-0} = label{11-0};
 }
 
-let hasSideEffects = 1 in {
+let hasSideEffects = 0, isReMaterializable = 1 in
 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
                     4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
 
+let hasSideEffects = 1 in
 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
                       (ins i32imm:$label, pred:$p),
                       4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
-}
 
 //===----------------------------------------------------------------------===//
 //  Control Flow Instructions.

Added: llvm/trunk/test/CodeGen/ARM/adr-hoist.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/adr-hoist.ll?rev=303053&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/adr-hoist.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/adr-hoist.ll Mon May 15 06:50:21 2017
@@ -0,0 +1,31 @@
+; RUN: llc -mtriple=armv7a   %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv7m %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv6m %s -o - | FileCheck %s
+
+ at arr = internal unnamed_addr constant [4 x i32] [i32 305419896, i32 -1430532899, i32 -2023406815, i32 -573785174], align 4
+
+; Check that the adr of arr is hoisted out of the loop
+; CHECK: adr [[REG:r[0-9]+]], .LCP
+; CHECK: .LBB
+; CHECK-NOT adr
+; CHECK: ldr{{(.w)?}} {{r[0-9]+}}, {{\[}}[[REG]],
+
+define void @fn(i32 %n, i32* %p) {
+entry:
+  %cmp8 = icmp sgt i32 %n, 0
+  br i1 %cmp8, label %for.body, label %for.cond.cleanup
+
+for.body:
+  %i.09 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds i32, i32* %p, i32 %i.09
+  %0 = load i32, i32* %arrayidx, align 4
+  %arrayidx1 = getelementptr inbounds [4 x i32], [4 x i32]* @arr, i32 0, i32 %0
+  %1 = load i32, i32* %arrayidx1, align 4
+  store i32 %1, i32* %arrayidx, align 4
+  %inc = add nuw nsw i32 %i.09, 1
+  %exitcond = icmp eq i32 %inc, %n
+  br i1 %exitcond, label %for.cond.cleanup, label %for.body
+
+for.cond.cleanup:
+  ret void
+}