[PATCH] D33076: [PPC] Move the combine "a << (b % (sizeof(a) * 8)) -> (PPCshl a, b)" to the backend. NFC.

[Tim Shen via Phabricator via llvm-commits]

timshen added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.h:122
+      /// amounts are supported - the actual bits shifted is the modulo result
+      /// of the amount and the element width.
       SRL, SRA, SHL,
----------------
efriedma wrote:
> Maybe leave the comment noting that 32-bit shifts are modulo 64?
Documented.

It's actually more subtle than "modulo 64". FWIW:

For (shl (i32 a), b):
    if ((b % 64) >= 32) return 0;
    return a << (b % 32)


https://reviews.llvm.org/D33076