[llvm] r301939 - Remove "_NC" suffix and semantics from TLSDESC_LD{64, 32}_LO12 and
Zachary Turner via llvm-commits
llvm-commits at lists.llvm.org
Tue May 2 11:05:04 PDT 2017
Hi Joel,
I had to revert this because it was breaking compilation.
Example errors:
D:\src\llvm-mono\lld\ELF\Target.cpp(1379): note: see usage of
'R_AARCH64_TLSDESC_ADD_LO12_NC'
D:\src\llvm-mono\lld\ELF\Target.cpp(1380): error C2065:
'R_AARCH64_TLSDESC_LD64_LO12_NC': undeclared identifier
D:\src\llvm-mono\lld\ELF\Target.cpp(1380): error C2131: expression did not
evaluate to a constant
D:\src\llvm-mono\lld\ELF\Target.cpp(1380): note: failure was caused by
non-constant arguments or reference to a non-constant symbol
D:\src\llvm-mono\lld\ELF\Target.cpp(1380): note: see usage of
'R_AARCH64_TLSDESC_LD64_LO12_NC'
D:\src\llvm-mono\lld\ELF\Target.cpp(1379): error C2051: case expression not
constant
D:\src\llvm-mono\lld\ELF\Target.cpp(1380): error C2051: case expression not
constant
D:\src\llvm-mono\lld\ELF\Target.cpp(1506): error C2065:
'R_AARCH64_TLSDESC_LD64_LO12_NC': undeclared identifier
D:\src\llvm-mono\lld\ELF\Target.cpp(1506): error C2131: expression did not
evaluate to a constant
D:\src\llvm-mono\lld\ELF\Target.cpp(1506): note: failure was caused by
non-constant arguments or reference to a non-constant symbol
D:\src\llvm-mono\lld\ELF\Target.cpp(1506): note: see usage of
'R_AARCH64_TLSDESC_LD64_LO12_NC'
D:\src\llvm-mono\lld\ELF\Target.cpp(1546): error C2065:
'R_AARCH64_TLSDESC_ADD_LO12_NC': undeclared identifier
D:\src\llvm-mono\lld\ELF\Target.cpp(1546): error C2131: expression did not
evaluate to a constant
D:\src\llvm-mono\lld\ELF\Target.cpp(1546): note: failure was caused by
non-constant arguments or reference to a non-constant symbol
D:\src\llvm-mono\lld\ELF\Target.cpp(1546): note: see usage of
'R_AARCH64_TLSDESC_ADD_LO12_NC'
D:\src\llvm-mono\lld\ELF\Target.cpp(1506): error C2051: case expression not
constant
D:\src\llvm-mono\lld\ELF\Target.cpp(1546): error C2051: case expression not
constant
D:\src\llvm-mono\lld\ELF\Target.cpp(1570): error C2065:
'R_AARCH64_TLSDESC_ADD_LO12_NC': undeclared identifier
D:\src\llvm-mono\lld\ELF\Target.cpp(1570): error C2131: expression did not
evaluate to a constant
D:\src\llvm-mono\lld\ELF\Target.cpp(1570): note: failure was caused by
non-constant arguments or reference to a non-c
But there were many more as well. Please resubmit after fixing these up.
On Tue, May 2, 2017 at 10:27 AM Joel Jones via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
> Author: joel_k_jones
> Date: Tue May 2 12:14:31 2017
> New Revision: 301939
>
> URL: http://llvm.org/viewvc/llvm-project?rev=301939&view=rev
> Log:
> Remove "_NC" suffix and semantics from TLSDESC_LD{64,32}_LO12 and
> TLSDESC_ADD_LO12 relocations
> Rearrange ordering in AArch64.def to follow relocation encoding
> Fix name:
> R_AARCH64_P32_LD64_GOT_LO12_NC => R_AARCH64_P32_LD32_GOT_LO12_NC
> Add support for several "TLS", "TLSGD", and "TLSLD" relocations for
> ILP32
> Fix return values from isNonILP32reloc
> Add implementations for
> R_AARCH64_ADR_PREL_PG_HI21_NC, R_AARCH64_P32_LD32_GOT_LO12_NC,
> R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC,
> R_AARCH64_P32_TLSDESC_LD32_LO12, R_AARCH64_LD64_GOT_LO12_NC,
> *TLSLD_LDST128_DTPREL_LO12, *TLSLD_LDST128_DTPREL_LO12_NC,
> *TLSLE_LDST128_TPREL_LO12, *TLSLE_LDST128_TPREL_LO12_NC
> Modify error messages to give name of equivalent relocation in the
> ABI not being used, along with better checking for non-existent
> requested relocations.
> Added assembler support for "pg_hi21_nc"
> Relocation definitions added without implementations:
> R_AARCH64_P32_TLSDESC_ADR_PREL21, R_AARCH64_P32_TLSGD_ADR_PREL21,
> R_AARCH64_P32_TLSGD_ADD_LO12_NC, R_AARCH64_P32_TLSLD_ADR_PREL21,
> R_AARCH64_P32_TLSLD_ADR_PAGE21, R_AARCH64_P32_TLSLD_ADD_LO12_NC,
> R_AARCH64_P32_TLSLD_LD_PREL19, R_AARCH64_P32_TLSDESC_LD_PREL19,
> R_AARCH64_P32_TLSGD_ADR_PAGE21, R_AARCH64_P32_TLS_DTPREL,
> R_AARCH64_P32_TLS_DTPMOD, R_AARCH64_P32_TLS_TPREL,
> R_AARCH64_P32_TLSDESC
> Fix encoding:
> R_AARCH64_P32_TLSDESC_ADR_PAGE21
>
> Reviewers: Peter Smith
>
> Patch by: Joel Jones (jjones at cavium.com)
>
> Differential Revision: https://reviews.llvm.org/D32072
>
> Added:
> llvm/trunk/test/MC/AArch64/arm32-large-relocs.s
> llvm/trunk/test/MC/AArch64/arm32-tls-relocs.s
> llvm/trunk/test/MC/AArch64/elf-reloc-pcreladdressing-ilp32.s
> llvm/trunk/test/MC/AArch64/lp64-diagnostics.s
> Modified:
> llvm/trunk/include/llvm/Support/ELFRelocs/AArch64.def
> llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp
> llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
> llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.cpp
> llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h
> llvm/trunk/test/CodeGen/AArch64/arm64-tls-dynamics.ll
> llvm/trunk/test/MC/AArch64/adrp-relocation.s
> llvm/trunk/test/MC/AArch64/arm32-elf-relocs.s
> llvm/trunk/test/MC/AArch64/arm64-elf-reloc-condbr.s
> llvm/trunk/test/MC/AArch64/arm64-elf-relocs.s
> llvm/trunk/test/MC/AArch64/arm64-tls-relocs.s
> llvm/trunk/test/MC/AArch64/elf-reloc-ldrlit.s
> llvm/trunk/test/MC/AArch64/elf-reloc-tstb.s
> llvm/trunk/test/MC/AArch64/elf-reloc-uncondbrimm.s
> llvm/trunk/test/MC/AArch64/error-location.s
> llvm/trunk/test/MC/AArch64/ilp32-diagnostics.s
> llvm/trunk/test/MC/AArch64/inline-asm-modifiers.s
> llvm/trunk/test/MC/AArch64/tls-relocs.s
> llvm/trunk/test/tools/llvm-readobj/reloc-types.test
>
> Modified: llvm/trunk/include/llvm/Support/ELFRelocs/AArch64.def
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ELFRelocs/AArch64.def?rev=301939&r1=301938&r2=301939&view=diff
>
> ==============================================================================
> --- llvm/trunk/include/llvm/Support/ELFRelocs/AArch64.def (original)
> +++ llvm/trunk/include/llvm/Support/ELFRelocs/AArch64.def Tue May 2
> 12:14:31 2017
> @@ -109,8 +109,8 @@ ELF_RELOC(R_AARCH64_TLSLE_LDST64_TPREL_L
> ELF_RELOC(R_AARCH64_TLSDESC_LD_PREL19, 0x230)
> ELF_RELOC(R_AARCH64_TLSDESC_ADR_PREL21, 0x231)
> ELF_RELOC(R_AARCH64_TLSDESC_ADR_PAGE21, 0x232)
> -ELF_RELOC(R_AARCH64_TLSDESC_LD64_LO12_NC, 0x233)
> -ELF_RELOC(R_AARCH64_TLSDESC_ADD_LO12_NC, 0x234)
> +ELF_RELOC(R_AARCH64_TLSDESC_LD64_LO12, 0x233)
> +ELF_RELOC(R_AARCH64_TLSDESC_ADD_LO12, 0x234)
> ELF_RELOC(R_AARCH64_TLSDESC_OFF_G1, 0x235)
> ELF_RELOC(R_AARCH64_TLSDESC_OFF_G0_NC, 0x236)
> ELF_RELOC(R_AARCH64_TLSDESC_LDR, 0x237)
> @@ -144,21 +144,28 @@ ELF_RELOC(R_AARCH64_P32_ADR_PREL_LO21,
> ELF_RELOC(R_AARCH64_P32_ADR_PREL_PG_HI21, 0x00b)
> ELF_RELOC(R_AARCH64_P32_ADD_ABS_LO12_NC, 0x00c)
> ELF_RELOC(R_AARCH64_P32_LDST8_ABS_LO12_NC, 0x00d)
> +ELF_RELOC(R_AARCH64_P32_LDST16_ABS_LO12_NC, 0x00e)
> +ELF_RELOC(R_AARCH64_P32_LDST32_ABS_LO12_NC, 0x00f)
> +ELF_RELOC(R_AARCH64_P32_LDST64_ABS_LO12_NC, 0x010)
> +ELF_RELOC(R_AARCH64_P32_LDST128_ABS_LO12_NC, 0x011)
> ELF_RELOC(R_AARCH64_P32_TSTBR14, 0x012)
> ELF_RELOC(R_AARCH64_P32_CONDBR19, 0x013)
> ELF_RELOC(R_AARCH64_P32_JUMP26, 0x014)
> ELF_RELOC(R_AARCH64_P32_CALL26, 0x015)
> -ELF_RELOC(R_AARCH64_P32_LDST16_ABS_LO12_NC, 0x00e)
> -ELF_RELOC(R_AARCH64_P32_LDST32_ABS_LO12_NC, 0x00f)
> -ELF_RELOC(R_AARCH64_P32_LDST64_ABS_LO12_NC, 0x010)
> ELF_RELOC(R_AARCH64_P32_MOVW_PREL_G0, 0x016)
> ELF_RELOC(R_AARCH64_P32_MOVW_PREL_G0_NC, 0x017)
> ELF_RELOC(R_AARCH64_P32_MOVW_PREL_G1, 0x018)
> -ELF_RELOC(R_AARCH64_P32_LDST128_ABS_LO12_NC, 0x011)
> ELF_RELOC(R_AARCH64_P32_GOT_LD_PREL19, 0x019)
> ELF_RELOC(R_AARCH64_P32_ADR_GOT_PAGE, 0x01a)
> -ELF_RELOC(R_AARCH64_P32_LD64_GOT_LO12_NC, 0x01b)
> +ELF_RELOC(R_AARCH64_P32_LD32_GOT_LO12_NC, 0x01b)
> ELF_RELOC(R_AARCH64_P32_LD32_GOTPAGE_LO14, 0x01c)
> +ELF_RELOC(R_AARCH64_P32_TLSGD_ADR_PREL21, 0x050)
> +ELF_RELOC(R_AARCH64_P32_TLSGD_ADR_PAGE21, 0x051)
> +ELF_RELOC(R_AARCH64_P32_TLSGD_ADD_LO12_NC, 0x052)
> +ELF_RELOC(R_AARCH64_P32_TLSLD_ADR_PREL21, 0x053)
> +ELF_RELOC(R_AARCH64_P32_TLSLD_ADR_PAGE21, 0x054)
> +ELF_RELOC(R_AARCH64_P32_TLSLD_ADD_LO12_NC, 0x055)
> +ELF_RELOC(R_AARCH64_P32_TLSLD_LD_PREL19, 0x056)
> ELF_RELOC(R_AARCH64_P32_TLSLD_MOVW_DTPREL_G1, 0x057)
> ELF_RELOC(R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0, 0x058)
> ELF_RELOC(R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0_NC, 0x059)
> @@ -173,6 +180,8 @@ ELF_RELOC(R_AARCH64_P32_TLSLD_LDST32_DTP
> ELF_RELOC(R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC, 0x062)
> ELF_RELOC(R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12, 0x063)
> ELF_RELOC(R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12_NC, 0x064)
> +ELF_RELOC(R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12, 0x065)
> +ELF_RELOC(R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12_NC,0x066)
> ELF_RELOC(R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21, 0x067)
> ELF_RELOC(R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC, 0x068)
> ELF_RELOC(R_AARCH64_P32_TLSIE_LD_GOTTPREL_PREL19, 0x069)
> @@ -190,12 +199,20 @@ ELF_RELOC(R_AARCH64_P32_TLSLE_LDST32_TPR
> ELF_RELOC(R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC, 0x075)
> ELF_RELOC(R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12, 0x076)
> ELF_RELOC(R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC, 0x077)
> -ELF_RELOC(R_AARCH64_P32_TLSDESC_ADR_PAGE21, 0x051)
> -ELF_RELOC(R_AARCH64_P32_TLSDESC_LD32_LO12_NC, 0x07d)
> -ELF_RELOC(R_AARCH64_P32_TLSDESC_ADD_LO12_NC, 0x034)
> +ELF_RELOC(R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12, 0x078)
> +ELF_RELOC(R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12_NC, 0x079)
> +ELF_RELOC(R_AARCH64_P32_TLSDESC_LD_PREL19, 0x07a)
> +ELF_RELOC(R_AARCH64_P32_TLSDESC_ADR_PREL21, 0x07b)
> +ELF_RELOC(R_AARCH64_P32_TLSDESC_ADR_PAGE21, 0x07c)
> +ELF_RELOC(R_AARCH64_P32_TLSDESC_LD32_LO12, 0x07d)
> +ELF_RELOC(R_AARCH64_P32_TLSDESC_ADD_LO12, 0x07e)
> ELF_RELOC(R_AARCH64_P32_TLSDESC_CALL, 0x07f)
> ELF_RELOC(R_AARCH64_P32_COPY, 0x0b4)
> ELF_RELOC(R_AARCH64_P32_GLOB_DAT, 0x0b5)
> ELF_RELOC(R_AARCH64_P32_JUMP_SLOT, 0x0b6)
> ELF_RELOC(R_AARCH64_P32_RELATIVE, 0x0b7)
> +ELF_RELOC(R_AARCH64_P32_TLS_DTPREL, 0x0b8)
> +ELF_RELOC(R_AARCH64_P32_TLS_DTPMOD, 0x0b9)
> +ELF_RELOC(R_AARCH64_P32_TLS_TPREL, 0x0ba)
> +ELF_RELOC(R_AARCH64_P32_TLSDESC, 0x0bb)
> ELF_RELOC(R_AARCH64_P32_IRELATIVE, 0x0bc)
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp?rev=301939&r1=301938&r2=301939&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp Tue May 2
> 12:14:31 2017
> @@ -580,8 +580,7 @@ void AArch64AsmPrinter::EmitInstruction(
> const MachineOperand &MO_Sym = MI->getOperand(0);
> MachineOperand MO_TLSDESC_LO12(MO_Sym), MO_TLSDESC(MO_Sym);
> MCOperand Sym, SymTLSDescLo12, SymTLSDesc;
> - MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS |
> AArch64II::MO_PAGEOFF |
> - AArch64II::MO_NC);
> + MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS |
> AArch64II::MO_PAGEOFF);
> MO_TLSDESC.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGE);
> MCInstLowering.lowerOperand(MO_Sym, Sym);
> MCInstLowering.lowerOperand(MO_TLSDESC_LO12, SymTLSDescLo12);
>
> Modified:
> llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp?rev=301939&r1=301938&r2=301939&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
> (original)
> +++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
> Tue May 2 12:14:31 2017
> @@ -69,34 +69,34 @@ static bool isNonILP32reloc(const MCFixu
> return true;
> case AArch64MCExpr::VK_ABS_G2_S:
> Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G2));
> - return ELF::R_AARCH64_NONE;
> + return true;
> case AArch64MCExpr::VK_ABS_G2_NC:
> Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2_NC));
> - return ELF::R_AARCH64_NONE;
> + return true;
> case AArch64MCExpr::VK_ABS_G1_S:
> Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G1));
> - return ELF::R_AARCH64_NONE;
> + return true;
> case AArch64MCExpr::VK_ABS_G1_NC:
> Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G1_NC));
> - return ELF::R_AARCH64_NONE;
> + return true;
> case AArch64MCExpr::VK_DTPREL_G2:
> Ctx.reportError(Fixup.getLoc(),
> BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G2));
> - return ELF::R_AARCH64_NONE;
> + return true;
> case AArch64MCExpr::VK_DTPREL_G1_NC:
> Ctx.reportError(Fixup.getLoc(),
> BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G1_NC));
> - return ELF::R_AARCH64_NONE;
> + return true;
> case AArch64MCExpr::VK_TPREL_G2:
> Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G2));
> - return ELF::R_AARCH64_NONE;
> + return true;
> case AArch64MCExpr::VK_TPREL_G1_NC:
> Ctx.reportError(Fixup.getLoc(),
> BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G1_NC));
> - return ELF::R_AARCH64_NONE;
> + return true;
> case AArch64MCExpr::VK_GOTTPREL_G1:
> Ctx.reportError(Fixup.getLoc(),
> BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G1));
> - return ELF::R_AARCH64_NONE;
> + return true;
> case AArch64MCExpr::VK_GOTTPREL_G0_NC:
> Ctx.reportError(Fixup.getLoc(),
> BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G0_NC));
> - return ELF::R_AARCH64_NONE;
> + return true;
> default: return false;
> }
> return false;
> @@ -141,6 +141,16 @@ unsigned AArch64ELFObjectWriter::getRelo
> case AArch64::fixup_aarch64_pcrel_adrp_imm21:
> if (SymLoc == AArch64MCExpr::VK_ABS && !IsNC)
> return R_CLS(ADR_PREL_PG_HI21);
> + if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) {
> + if (IsILP32) {
> + Ctx.reportError(Fixup.getLoc(),
> + "invalid fixup for 32-bit pcrel ADRP
> instruction "
> + "VK_ABS VK_NC");
> + return ELF::R_AARCH64_NONE;
> + } else {
> + return ELF::R_AARCH64_ADR_PREL_PG_HI21_NC;
> + }
> + }
> if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC)
> return R_CLS(ADR_GOT_PAGE);
> if (SymLoc == AArch64MCExpr::VK_GOTTPREL && !IsNC)
> @@ -179,7 +189,8 @@ unsigned AArch64ELFObjectWriter::getRelo
> return R_CLS(ABS32);
> case FK_Data_8:
> if (IsILP32) {
> - Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(ABS64));
> + Ctx.reportError(Fixup.getLoc(), "ILP32 8 byte absolute data "
> + "relocation not supported (LP64 eqv: ABS64)");
> return ELF::R_AARCH64_NONE;
> } else
> return ELF::R_AARCH64_ABS64;
> @@ -197,7 +208,7 @@ unsigned AArch64ELFObjectWriter::getRelo
> if (RefKind == AArch64MCExpr::VK_TPREL_LO12)
> return R_CLS(TLSLE_ADD_TPREL_LO12);
> if (RefKind == AArch64MCExpr::VK_TLSDESC_LO12)
> - return R_CLS(TLSDESC_ADD_LO12_NC);
> + return R_CLS(TLSDESC_ADD_LO12);
> if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
> return R_CLS(ADD_ABS_LO12_NC);
>
> @@ -245,15 +256,67 @@ unsigned AArch64ELFObjectWriter::getRelo
> return R_CLS(TLSLE_LDST32_TPREL_LO12);
> if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
> return R_CLS(TLSLE_LDST32_TPREL_LO12_NC);
> + if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) {
> + if (IsILP32) {
> + return ELF::R_AARCH64_P32_LD32_GOT_LO12_NC;
> + } else {
> + Ctx.reportError(Fixup.getLoc(),
> + "LP64 4 byte unchecked GOT load/store
> relocation "
> + "not supported (ILP32 eqv: LD32_GOT_LO12_NC");
> + return ELF::R_AARCH64_NONE;
> + }
> + }
> + if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC) {
> + if (IsILP32) {
> + Ctx.reportError(Fixup.getLoc(),
> + "ILP32 4 byte checked GOT load/store relocation
> "
> + "not supported (unchecked eqv:
> LD32_GOT_LO12_NC)");
> + } else {
> + Ctx.reportError(Fixup.getLoc(),
> + "LP64 4 byte checked GOT load/store relocation "
> + "not supported (unchecked/ILP32 eqv: "
> + "LD32_GOT_LO12_NC)");
> + }
> + return ELF::R_AARCH64_NONE;
> + }
> + if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) {
> + if (IsILP32) {
> + return ELF::R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC;
> + } else {
> + Ctx.reportError(Fixup.getLoc(), "LP64 32-bit load/store "
> + "relocation not supported (ILP32 eqv: "
> + "TLSIE_LD32_GOTTPREL_LO12_NC)");
> + return ELF::R_AARCH64_NONE;
> + }
> + }
> + if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC) {
> + if (IsILP32) {
> + return ELF::R_AARCH64_P32_TLSDESC_LD32_LO12;
> + } else {
> + Ctx.reportError(Fixup.getLoc(),
> + "LP64 4 byte TLSDESC load/store relocation "
> + "not supported (ILP32 eqv: TLSDESC_LD64_LO12)");
> + return ELF::R_AARCH64_NONE;
> + }
> + }
>
> Ctx.reportError(Fixup.getLoc(),
> - "invalid fixup for 32-bit load/store instruction");
> + "invalid fixup for 32-bit load/store instruction "
> + "fixup_aarch64_ldst_imm12_scale4");
> return ELF::R_AARCH64_NONE;
> case AArch64::fixup_aarch64_ldst_imm12_scale8:
> if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
> return R_CLS(LDST64_ABS_LO12_NC);
> - if (SymLoc == AArch64MCExpr::VK_GOT && IsNC)
> - return R_CLS(LD64_GOT_LO12_NC);
> + if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) {
> + if (!IsILP32) {
> + return ELF::R_AARCH64_LD64_GOT_LO12_NC;
> + } else {
> + Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
> + "relocation not supported (LP64 eqv: "
> + "LD64_GOT_LO12_NC)");
> + return ELF::R_AARCH64_NONE;
> + }
> + }
> if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
> return R_CLS(TLSLD_LDST64_DTPREL_LO12);
> if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
> @@ -262,19 +325,40 @@ unsigned AArch64ELFObjectWriter::getRelo
> return R_CLS(TLSLE_LDST64_TPREL_LO12);
> if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
> return R_CLS(TLSLE_LDST64_TPREL_LO12_NC);
> - if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC)
> - return IsILP32 ? ELF::R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC
> - : ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
> - if (SymLoc == AArch64MCExpr::VK_TLSDESC && IsNC)
> - return IsILP32 ? ELF::R_AARCH64_P32_TLSDESC_LD32_LO12_NC
> - : ELF::R_AARCH64_TLSDESC_LD64_LO12_NC;
> -
> + if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) {
> + if (!IsILP32) {
> + return ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
> + } else {
> + Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
> + "relocation not supported (LP64 eqv: "
> + "TLSIE_LD64_GOTTPREL_LO12_NC)");
> + return ELF::R_AARCH64_NONE;
> + }
> + }
> + if (SymLoc == AArch64MCExpr::VK_TLSDESC) {
> + if (!IsILP32) {
> + return ELF::R_AARCH64_TLSDESC_LD64_LO12;
> + } else {
> + Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
> + "relocation not supported (LP64 eqv: "
> + "TLSDESC_LD64_LO12)");
> + return ELF::R_AARCH64_NONE;
> + }
> + }
> Ctx.reportError(Fixup.getLoc(),
> "invalid fixup for 64-bit load/store instruction");
> return ELF::R_AARCH64_NONE;
> case AArch64::fixup_aarch64_ldst_imm12_scale16:
> if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
> return R_CLS(LDST128_ABS_LO12_NC);
> + if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
> + return R_CLS(TLSLD_LDST128_DTPREL_LO12);
> + if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
> + return R_CLS(TLSLD_LDST128_DTPREL_LO12_NC);
> + if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
> + return R_CLS(TLSLE_LDST128_TPREL_LO12);
> + if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
> + return R_CLS(TLSLE_LDST128_TPREL_LO12_NC);
>
> Ctx.reportError(Fixup.getLoc(),
> "invalid fixup for 128-bit load/store instruction");
>
> Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.cpp?rev=301939&r1=301938&r2=301939&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.cpp Tue May
> 2 12:14:31 2017
> @@ -62,6 +62,7 @@ StringRef AArch64MCExpr::getVariantKindN
> case VK_TPREL_LO12_NC: return ":tprel_lo12_nc:";
> case VK_TLSDESC_LO12: return ":tlsdesc_lo12:";
> case VK_ABS_PAGE: return "";
> + case VK_ABS_PAGE_NC: return ":pg_hi21_nc:";
> case VK_GOT_PAGE: return ":got:";
> case VK_GOT_LO12: return ":got_lo12:";
> case VK_GOTTPREL_PAGE: return ":gottprel:";
>
> Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h?rev=301939&r1=301938&r2=301939&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h (original)
> +++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h Tue May 2
> 12:14:31 2017
> @@ -62,6 +62,7 @@ public:
> // since a user would write ":lo12:").
> VK_CALL = VK_ABS,
> VK_ABS_PAGE = VK_ABS | VK_PAGE,
> + VK_ABS_PAGE_NC = VK_ABS | VK_PAGE | VK_NC,
> VK_ABS_G3 = VK_ABS | VK_G3,
> VK_ABS_G2 = VK_ABS | VK_G2,
> VK_ABS_G2_S = VK_SABS | VK_G2,
> @@ -95,7 +96,7 @@ public:
> VK_TPREL_HI12 = VK_TPREL | VK_HI12,
> VK_TPREL_LO12 = VK_TPREL | VK_PAGEOFF,
> VK_TPREL_LO12_NC = VK_TPREL | VK_PAGEOFF | VK_NC,
> - VK_TLSDESC_LO12 = VK_TLSDESC | VK_PAGEOFF | VK_NC,
> + VK_TLSDESC_LO12 = VK_TLSDESC | VK_PAGEOFF,
> VK_TLSDESC_PAGE = VK_TLSDESC | VK_PAGE,
>
> VK_INVALID = 0xfff
>
> Modified: llvm/trunk/test/CodeGen/AArch64/arm64-tls-dynamics.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-tls-dynamics.ll?rev=301939&r1=301938&r2=301939&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/arm64-tls-dynamics.ll (original)
> +++ llvm/trunk/test/CodeGen/AArch64/arm64-tls-dynamics.ll Tue May 2
> 12:14:31 2017
> @@ -30,13 +30,13 @@ define i32 @test_generaldynamic() {
> ; CHECK-NOLD: ldr w0, [x[[TP]], x0]
>
> ; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
> -; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
> -; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
> +; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12
> +; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12
> ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL
>
> ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
> -; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
> -; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
> +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12
> +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12
> ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL
>
> }
> @@ -56,13 +56,13 @@ define i32* @test_generaldynamic_addr()
> ; CHECK: add x0, [[TP]], x0
>
> ; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
> -; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
> -; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
> +; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12
> +; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12
> ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL
>
> ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
> -; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
> -; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
> +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12
> +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12
> ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL
>
> }
> @@ -95,15 +95,15 @@ define i32 @test_localdynamic() {
>
>
> ; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
> -; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
> -; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
> +; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12
> +; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12
> ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL
> ; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_HI12
> ; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
>
> ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
> -; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
> -; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
> +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12
> +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12
> ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL
>
> }
> @@ -131,15 +131,15 @@ define i32* @test_localdynamic_addr() {
> ret i32* @local_dynamic_var
>
> ; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
> -; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
> -; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
> +; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12
> +; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12
> ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL
> ; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_HI12
> ; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
>
> ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
> -; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
> -; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
> +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12
> +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12
> ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL
> }
>
>
> Modified: llvm/trunk/test/MC/AArch64/adrp-relocation.s
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/adrp-relocation.s?rev=301939&r1=301938&r2=301939&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/MC/AArch64/adrp-relocation.s (original)
> +++ llvm/trunk/test/MC/AArch64/adrp-relocation.s Tue May 2 12:14:31 2017
> @@ -1,4 +1,6 @@
> // RUN: llvm-mc -triple=aarch64-linux-gnu -filetype=obj -o - %s|
> llvm-readobj -r - | FileCheck %s
> +// RUN: llvm-mc -target-abi=ilp32 -triple=aarch64-linux-gnu -filetype=obj
> \
> +// RUN: -o - %s| llvm-readobj -r - | FileCheck -check-prefix=CHECK-ILP32
> %s
> .text
> // These should produce an ADRP/ADD pair to calculate the address of
> // testfn. The important point is that LLVM shouldn't think it can deal
> with the
> @@ -16,3 +18,7 @@ sym:
> // CHECK: R_AARCH64_ADR_GOT_PAGE sym
> // CHECK: R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 sym
> // CHECK: R_AARCH64_TLSDESC_ADR_PAGE21 sym
> +// CHECK-ILP32: R_AARCH64_P32_ADR_PREL_PG_HI21 sym
> +// CHECK-ILP32: R_AARCH64_P32_ADR_GOT_PAGE sym
> +// CHECK-ILP32: R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21 sym
> +// CHECK-ILP32: R_AARCH64_P32_TLSDESC_ADR_PAGE21 sym
>
> Modified: llvm/trunk/test/MC/AArch64/arm32-elf-relocs.s
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm32-elf-relocs.s?rev=301939&r1=301938&r2=301939&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/MC/AArch64/arm32-elf-relocs.s (original)
> +++ llvm/trunk/test/MC/AArch64/arm32-elf-relocs.s Tue May 2 12:14:31 2017
> @@ -1,4 +1,7 @@
> -// RUN: llvm-mc -triple=arm64-linux-gnu -o - < %s | FileCheck %s
> +// RUN: llvm-mc -target-abi=ilp32 -triple=arm64-linux-gnu -o - < %s | \
> +// RUN: FileCheck %s
> +// RUN: llvm-mc -target-abi=ilp32 -triple=arm64-linux-gnu -show-encoding \
> +// RUN: -o - < %s | FileCheck --check-prefix=CHECK-ENCODING %s
> // RUN: llvm-mc -target-abi=ilp32 -triple=arm64-linux-gnu -filetype=obj <
> %s | \
> // RUN: llvm-objdump -triple=arm64-linux-gnu - -r | \
> // RUN: FileCheck %s --check-prefix=CHECK-OBJ-ILP32
> @@ -25,7 +28,7 @@
>
> add x5, x0, #:tlsdesc_lo12:sym
> // CHECK: add x5, x0, :tlsdesc_lo12:sym
> -// CHECK-OBJ-ILP32: 14 R_AARCH64_P32_TLSDESC_ADD_LO12_NC sym
> +// CHECK-OBJ-ILP32: 14 R_AARCH64_P32_TLSDESC_ADD_LO12 sym
>
> add x0, x2, #:lo12:sym+8
> // CHECK: add x0, x2, :lo12:sym
> @@ -49,33 +52,33 @@
>
> add x5, x0, #:tlsdesc_lo12:sym+70
> // CHECK: add x5, x0, :tlsdesc_lo12:sym+70
> -// CHECK-OBJ-ILP32: 2c R_AARCH64_P32_TLSDESC_ADD_LO12_NC sym+70
> +// CHECK-OBJ-ILP32: 2c R_AARCH64_P32_TLSDESC_ADD_LO12 sym+70
>
> .hword sym + 4 - .
> // CHECK-OBJ-ILP32: 30 R_AARCH64_P32_PREL16 sym+4
> .word sym - . + 8
> -// CHECK-OBJ-ILP32 32 R_AARCH64_P32_PREL32 sym+8
> +// CHECK-OBJ-ILP32: 32 R_AARCH64_P32_PREL32 sym+8
>
> .hword sym
> -// CHECK-OBJ-ILP32 3e R_AARCH64_P32_ABS16 sym
> +// CHECK-OBJ-ILP32: 36 R_AARCH64_P32_ABS16 sym
> .word sym+1
> -// CHECK-OBJ-ILP32 40 R_AARCH64_P32_ABS32 sym+1
> +// CHECK-OBJ-ILP32: 38 R_AARCH64_P32_ABS32 sym+1
>
> adrp x0, sym
> // CHECK: adrp x0, sym
> -// CHECK-OBJ-ILP32 4c R_AARCH64_P32_ADR_PREL_PG_HI21 sym
> +// CHECK-OBJ-ILP32: 3c R_AARCH64_P32_ADR_PREL_PG_HI21 sym
>
> adrp x15, :got:sym
> // CHECK: adrp x15, :got:sym
> -// CHECK-OBJ-ILP32 50 R_AARCH64_P32_ADR_GOT_PAGE sym
> +// CHECK-OBJ-ILP32: 40 R_AARCH64_P32_ADR_GOT_PAGE sym
>
> adrp x29, :gottprel:sym
> // CHECK: adrp x29, :gottprel:sym
> -// CHECK-OBJ-ILP32 54 R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21 sym
> +// CHECK-OBJ-ILP32: 44 R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21 sym
>
> adrp x2, :tlsdesc:sym
> // CHECK: adrp x2, :tlsdesc:sym
> -// CHECK-OBJ-ILP32 58 R_AARCH64_P32_TLSDESC_ADR_PAGE21 sym
> +// CHECK-OBJ-ILP32: 48 R_AARCH64_P32_TLSDESC_ADR_PAGE21 sym
>
> // LLVM is not competent enough to do this relocation because the
> // page boundary could occur anywhere after linking. A relocation
> @@ -84,7 +87,7 @@
> .global trickQuestion
> trickQuestion:
> // CHECK: adrp x3, trickQuestion
> -// CHECK-OBJ-ILP32 5c R_AARCH64_P32_ADR_PREL_PG_HI21 trickQuestion
> +// CHECK-OBJ-ILP32: 4c R_AARCH64_P32_ADR_PREL_PG_HI21 trickQuestion
>
> ldrb w2, [x3, :lo12:sym]
> ldrsb w5, [x7, #:lo12:sym]
> @@ -94,10 +97,10 @@ trickQuestion:
> // CHECK: ldrsb w5, [x7, :lo12:sym]
> // CHECK: ldrsb x11, [x13, :lo12:sym]
> // CHECK: ldr b17, [x19, :lo12:sym]
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST8_ABS_LO12_NC sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST8_ABS_LO12_NC sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST8_ABS_LO12_NC sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST8_ABS_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST8_ABS_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST8_ABS_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST8_ABS_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST8_ABS_LO12_NC sym
>
> ldrb w23, [x29, #:dtprel_lo12_nc:sym]
> ldrsb w23, [x19, #:dtprel_lo12:sym]
> @@ -107,10 +110,10 @@ trickQuestion:
> // CHECK: ldrsb w23, [x19, :dtprel_lo12:sym]
> // CHECK: ldrsb x17, [x13, :dtprel_lo12_nc:sym]
> // CHECK: ldr b11, [x7, :dtprel_lo12:sym]
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 sym
>
> ldrb w1, [x2, :tprel_lo12:sym]
> ldrsb w3, [x4, #:tprel_lo12_nc:sym]
> @@ -120,10 +123,10 @@ trickQuestion:
> // CHECK: ldrsb w3, [x4, :tprel_lo12_nc:sym]
> // CHECK: ldrsb x5, [x6, :tprel_lo12:sym]
> // CHECK: ldr b7, [x8, :tprel_lo12_nc:sym]
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC sym
>
> ldrh w2, [x3, #:lo12:sym]
> ldrsh w5, [x7, :lo12:sym]
> @@ -133,10 +136,10 @@ trickQuestion:
> // CHECK: ldrsh w5, [x7, :lo12:sym]
> // CHECK: ldrsh x11, [x13, :lo12:sym]
> // CHECK: ldr h17, [x19, :lo12:sym]
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST16_ABS_LO12_NC sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST16_ABS_LO12_NC sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST16_ABS_LO12_NC sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST16_ABS_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST16_ABS_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST16_ABS_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST16_ABS_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST16_ABS_LO12_NC sym
>
> ldrh w23, [x29, #:dtprel_lo12_nc:sym]
> ldrsh w23, [x19, :dtprel_lo12:sym]
> @@ -146,10 +149,10 @@ trickQuestion:
> // CHECK: ldrsh w23, [x19, :dtprel_lo12:sym]
> // CHECK: ldrsh x17, [x13, :dtprel_lo12_nc:sym]
> // CHECK: ldr h11, [x7, :dtprel_lo12:sym]
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 sym
>
> ldrh w1, [x2, :tprel_lo12:sym]
> ldrsh w3, [x4, #:tprel_lo12_nc:sym]
> @@ -159,10 +162,10 @@ trickQuestion:
> // CHECK: ldrsh w3, [x4, :tprel_lo12_nc:sym]
> // CHECK: ldrsh x5, [x6, :tprel_lo12:sym]
> // CHECK: ldr h7, [x8, :tprel_lo12_nc:sym]
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC sym
>
> ldr w1, [x2, #:lo12:sym]
> ldrsw x3, [x4, #:lo12:sym]
> @@ -170,9 +173,9 @@ trickQuestion:
> // CHECK: ldr w1, [x2, :lo12:sym]
> // CHECK: ldrsw x3, [x4, :lo12:sym]
> // CHECK: ldr s4, [x5, :lo12:sym]
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST32_ABS_LO12_NC sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST32_ABS_LO12_NC sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST32_ABS_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST32_ABS_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST32_ABS_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST32_ABS_LO12_NC sym
>
> ldr w1, [x2, :dtprel_lo12:sym]
> ldrsw x3, [x4, #:dtprel_lo12_nc:sym]
> @@ -180,9 +183,9 @@ trickQuestion:
> // CHECK: ldr w1, [x2, :dtprel_lo12:sym]
> // CHECK: ldrsw x3, [x4, :dtprel_lo12_nc:sym]
> // CHECK: ldr s4, [x5, :dtprel_lo12_nc:sym]
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12 sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12 sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC sym
>
>
> ldr w1, [x2, #:tprel_lo12:sym]
> @@ -191,53 +194,69 @@ trickQuestion:
> // CHECK: ldr w1, [x2, :tprel_lo12:sym]
> // CHECK: ldrsw x3, [x4, :tprel_lo12_nc:sym]
> // CHECK: ldr s4, [x5, :tprel_lo12_nc:sym]
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12 sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12 sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC sym
>
> ldr x28, [x27, :lo12:sym]
> - ldr d26, [x25, #:lo12:sym]
> + ldr d26, [x25, :lo12:sym]
> // CHECK: ldr x28, [x27, :lo12:sym]
> // CHECK: ldr d26, [x25, :lo12:sym]
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST64_ABS_LO12_NC sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST64_ABS_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST64_ABS_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST64_ABS_LO12_NC sym
>
> - ldr x24, [x23, #:got_lo12:sym]
> - ldr d22, [x21, :got_lo12:sym]
> -// CHECK: ldr x24, [x23, :got_lo12:sym]
> -// CHECK: ldr d22, [x21, :got_lo12:sym]
> -// CHECK-OBJ-ILP32 R_AARCH64_LD32_GOT_LO12_NC sym
> -// CHECK-OBJ-ILP32 R_AARCH64_LD32_GOT_LO12_NC sym
> + ldr w24, [x23, :got_lo12:sym]
> + ldr s22, [x21, :got_lo12:sym]
> +// CHECK: ldr w24, [x23, :got_lo12:sym]
> +// CHECK: ldr s22, [x21, :got_lo12:sym]
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_LD32_GOT_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_LD32_GOT_LO12_NC sym
>
> ldr x24, [x23, :dtprel_lo12_nc:sym]
> - ldr d22, [x21, #:dtprel_lo12:sym]
> + ldr d22, [x21, :dtprel_lo12:sym]
> // CHECK: ldr x24, [x23, :dtprel_lo12_nc:sym]
> // CHECK: ldr d22, [x21, :dtprel_lo12:sym]
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12_NC sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12 sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12 sym
>
> - ldr x24, [x23, #:tprel_lo12:sym]
> + ldr q24, [x23, :dtprel_lo12_nc:sym]
> + ldr q22, [x21, :dtprel_lo12:sym]
> +// CHECK: ldr q24, [x23, :dtprel_lo12_nc:sym]
> +// CHECK: ldr q22, [x21, :dtprel_lo12:sym]
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12 sym
> +
> + ldr x24, [x23, :tprel_lo12:sym]
> ldr d22, [x21, :tprel_lo12_nc:sym]
> // CHECK: ldr x24, [x23, :tprel_lo12:sym]
> // CHECK: ldr d22, [x21, :tprel_lo12_nc:sym]
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12 sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC sym
> -
> -# ldr x24, [x23, :gottprel_lo12:sym]
> -# ldr d22, [x21, #:gottprel_lo12:sym]
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12 sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC sym
>
> - ldr x24, [x23, #:tlsdesc_lo12:sym]
> - ldr d22, [x21, :tlsdesc_lo12:sym]
> -// CHECK: ldr x24, [x23, :tlsdesc_lo12:sym]
> -// CHECK: ldr d22, [x21, :tlsdesc_lo12:sym]
> -// Why is there a "_NC" at the end? "ELF for the ARM 64-bit architecture
> -// (AArch64) beta" doesn't have that.
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSDESC_LD32_LO12_NC sym
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSDESC_LD64_LO12_NC sym
> + ldr q24, [x23, :tprel_lo12:sym]
> + ldr q22, [x21, :tprel_lo12_nc:sym]
> +// CHECK: ldr q24, [x23, :tprel_lo12:sym]
> +// CHECK: ldr q22, [x21, :tprel_lo12_nc:sym]
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12 sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12_NC sym
> +
> + ldr w24, [x23, :gottprel_lo12:sym]
> + ldr s22, [x21, :gottprel_lo12:sym]
> +
> + ldr w24, [x23, :tlsdesc_lo12:sym]
> + ldr s22, [x21, :tlsdesc_lo12:sym]
> +// CHECK: ldr w24, [x23, :tlsdesc_lo12:sym]
> +// CHECK: ldr s22, [x21, :tlsdesc_lo12:sym]
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSDESC_LD32_LO12 sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSDESC_LD32_LO12 sym
>
> ldr q20, [x19, #:lo12:sym]
> // CHECK: ldr q20, [x19, :lo12:sym]
> -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST128_ABS_LO12_NC sym
> +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST128_ABS_LO12_NC sym
> +// check encoding here, since encoding test doesn't belong with TLS
> encoding
> +// tests, as it isn't a TLS relocation.
> +// CHECK-ENCODING: ldr q20, [x19, :lo12:sym] // encoding:
> [0x74,0bAAAAAA10,0b11AAAAAA,0x3d]
> +// CHECK-ENCODING-NEXT: 0, value: :lo12:sym, kind:
> fixup_aarch64_ldst_imm12_scale16
>
> // Since relocated instructions print without a '#', that syntax should
> // certainly be accepted when assembling.
>
> Added: llvm/trunk/test/MC/AArch64/arm32-large-relocs.s
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm32-large-relocs.s?rev=301939&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/MC/AArch64/arm32-large-relocs.s (added)
> +++ llvm/trunk/test/MC/AArch64/arm32-large-relocs.s Tue May 2 12:14:31
> 2017
> @@ -0,0 +1,31 @@
> +// RUN: llvm-mc -target-abi=ilp32 -triple=arm64-linux-gnu -show-encoding
> -o - \
> +// RUN: %s \
> +// RUN: | FileCheck %s
> +// RUN: llvm-mc -target-abi=ilp32 -triple=arm64-linux-gnu -show-encoding \
> +// RUN: -filetype=obj -o - %s \
> +// RUN: | llvm-objdump -r - \
> +// RUN: | FileCheck --check-prefix=CHECK-OBJ %s
> +
> + movz x2, #:abs_g0:sym
> + movk w3, #:abs_g0_nc:sym
> + movz x13, #:abs_g0_s:sym
> + movn x17, #:abs_g0_s:sym
> +// CHECK: movz x2, #:abs_g0:sym // encoding:
> [0bAAA00010,A,0b100AAAAA,0xd2]
> +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0:sym, kind:
> fixup_aarch64_movw
> +// CHECK: movk w3, #:abs_g0_nc:sym // encoding:
> [0bAAA00011,A,0b100AAAAA,0x72]
> +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_nc:sym, kind:
> fixup_aarch64_movw
> +// CHECK: movz x13, #:abs_g0_s:sym // encoding:
> [0bAAA01101,A,0b100AAAAA,0xd2]
> +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind:
> fixup_aarch64_movw
> +// CHECK: movn x17, #:abs_g0_s:sym // encoding:
> [0bAAA10001,A,0b100AAAAA,0x92]
> +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind:
> fixup_aarch64_movw
> +
> +// CHECK-OBJ: 0 R_AARCH64_P32_MOVW_UABS_G0 sym
> +// CHECK-OBJ: 4 R_AARCH64_P32_MOVW_UABS_G0_NC sym
> +// CHECK-OBJ: 8 R_AARCH64_P32_MOVW_SABS_G0 sym
> +// CHECK-OBJ: c R_AARCH64_P32_MOVW_SABS_G0 sym
> +
> + movz x4, #:abs_g1:sym
> +// CHECK: movz x4, #:abs_g1:sym // encoding:
> [0bAAA00100,A,0b101AAAAA,0xd2]
> +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1:sym, kind:
> fixup_aarch64_movw
> +
> +// CHECK-OBJ: 10 R_AARCH64_P32_MOVW_UABS_G1 sym
>
> Added: llvm/trunk/test/MC/AArch64/arm32-tls-relocs.s
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm32-tls-relocs.s?rev=301939&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/MC/AArch64/arm32-tls-relocs.s (added)
> +++ llvm/trunk/test/MC/AArch64/arm32-tls-relocs.s Tue May 2 12:14:31 2017
> @@ -0,0 +1,290 @@
> +// RUN: llvm-mc -target-abi=ilp32 -triple=arm64-none-linux-gnu \
> +// RUN: -show-encoding < %s | FileCheck --check-prefix=CHECK-ILP32 %s
> +// RUN: llvm-mc -target-abi=ilp32 -triple=arm64-none-linux-gnu \
> +// RUN: -filetype=obj < %s -o - | \
> +// RUN: llvm-readobj -r -t | FileCheck --check-prefix=CHECK-ELF-ILP32 %s
> +
>
> +////////////////////////////////////////////////////////////////////////////////
> +// TLS initial-exec forms
>
> +////////////////////////////////////////////////////////////////////////////////
> +
> + adrp x11, :gottprel:var
> + ldr w10, [x0, #:gottprel_lo12:var]
> + ldr w9, :gottprel:var
> +// CHECK-ILP32: adrp x11, :gottprel:var // encoding:
> [0x0b'A',A,A,0x90'A']
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :gottprel:var, kind: fixup_aarch64_pcrel_adrp_imm21
> +// CHECK-ILP32: ldr w10, [x0, :gottprel_lo12:var] // encoding:
> [0x0a,0bAAAAAA00,0b01AAAAAA,0xb9]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :gottprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale4
> +// CHECK-ILP32: ldr w9, :gottprel:var // encoding:
> [0bAAA01001,A,A,0x18]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :gottprel:var, kind: fixup_aarch64_ldr_pcrel_imm19
> +
> +// CHECK-ELF-ILP32: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21 [[VARSYM:[^ ]+]]
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC [[VARSYM]]
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSIE_LD_GOTTPREL_PREL19 [[VARSYM]]
> +
> +
>
> +////////////////////////////////////////////////////////////////////////////////
> +// TLS local-exec forms
>
> +////////////////////////////////////////////////////////////////////////////////
> +
> + movz x5, #:tprel_g1:var
> + movn x6, #:tprel_g1:var
> + movz w7, #:tprel_g1:var
> +// CHECK-ILP32: movz x5, #:tprel_g1:var // encoding:
> [0bAAA00101,A,0b101AAAAA,0x92]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw
> +// CHECK-ILP32: movn x6, #:tprel_g1:var // encoding:
> [0bAAA00110,A,0b101AAAAA,0x92]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw
> +// CHECK-ILP32: movz w7, #:tprel_g1:var // encoding:
> [0bAAA00111,A,0b101AAAAA,0x12]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw
> +
> +// CHECK-ELF-ILP32: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_MOVW_TPREL_G1
> [[VARSYM]]
> +// CHECK-ELF-ILP32: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_MOVW_TPREL_G1
> [[VARSYM]]
> +// CHECK-ELF-ILP32: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_MOVW_TPREL_G1
> [[VARSYM]]
> +
> +
> + movz x11, #:tprel_g0:var
> + movn x12, #:tprel_g0:var
> + movz w13, #:tprel_g0:var
> +// CHECK-ILP32: movz x11, #:tprel_g0:var // encoding:
> [0bAAA01011,A,0b100AAAAA,0x92]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw
> +// CHECK-ILP32: movn x12, #:tprel_g0:var // encoding:
> [0bAAA01100,A,0b100AAAAA,0x92]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw
> +// CHECK-ILP32: movz w13, #:tprel_g0:var // encoding:
> [0bAAA01101,A,0b100AAAAA,0x12]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw
> +
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLE_MOVW_TPREL_G0 [[VARSYM]]
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLE_MOVW_TPREL_G0 [[VARSYM]]
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLE_MOVW_TPREL_G0 [[VARSYM]]
> +
> +
> + movk w15, #:tprel_g0_nc:var
> + movk w16, #:tprel_g0_nc:var
> +// CHECK-ILP32: movk w15, #:tprel_g0_nc:var // encoding:
> [0bAAA01111,A,0b100AAAAA,0x72]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :tprel_g0_nc:var, kind: fixup_aarch64_movw
> +// CHECK-ILP32: movk w16, #:tprel_g0_nc:var // encoding:
> [0bAAA10000,A,0b100AAAAA,0x72]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :tprel_g0_nc:var, kind: fixup_aarch64_movw
> +
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]]
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]]
> +
> +
> + add x21, x22, #:tprel_lo12:var
> +// CHECK-ILP32: add x21, x22, :tprel_lo12:var // encoding:
> [0xd5,0bAAAAAA10,0b00AAAAAA,0x91]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_add_imm12
> +
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLE_ADD_TPREL_LO12 [[VARSYM]]
> +
> +
> + add x25, x26, #:tprel_lo12_nc:var
> +// CHECK-ILP32: add x25, x26, :tprel_lo12_nc:var // encoding:
> [0x59,0bAAAAAA11,0b00AAAAAA,0x91]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_add_imm12
> +
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC [[VARSYM]]
> +
> +
> + ldrb w29, [x30, #:tprel_lo12:var]
> + ldrsb x29, [x28, #:tprel_lo12_nc:var]
> +// CHECK-ILP32: ldrb w29, [x30, :tprel_lo12:var] // encoding:
> [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale1
> +// CHECK-ILP32: ldrsb x29, [x28, :tprel_lo12_nc:var] // encoding:
> [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale1
> +
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 [[VARSYM]]
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC [[VARSYM]]
> +
> +
> + strh w27, [x26, #:tprel_lo12:var]
> + ldrsh x25, [x24, #:tprel_lo12_nc:var]
> +// CHECK-ILP32: strh w27, [x26, :tprel_lo12:var] // encoding:
> [0x5b,0bAAAAAA11,0b00AAAAAA,0x79]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale2
> +// CHECK-ILP32: ldrsh x25, [x24, :tprel_lo12_nc:var] // encoding:
> [0x19,0bAAAAAA11,0b10AAAAAA,0x79]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale2
> +
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 [[VARSYM]]
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC [[VARSYM]]
> +
> +
> + ldr w23, [x22, #:tprel_lo12:var]
> + ldrsw x21, [x20, #:tprel_lo12_nc:var]
> +// CHECK-ILP32: ldr w23, [x22, :tprel_lo12:var] // encoding:
> [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale4
> +// CHECK-ILP32: ldrsw x21, [x20, :tprel_lo12_nc:var] // encoding:
> [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale4
> +
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12 [[VARSYM]]
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC [[VARSYM]]
> +
> + ldr x19, [x18, #:tprel_lo12:var]
> + str x17, [x16, #:tprel_lo12_nc:var]
> +// CHECK-ILP32: ldr x19, [x18, :tprel_lo12:var] // encoding:
> [0x53,0bAAAAAA10,0b01AAAAAA,0xf9]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8
> +// CHECK-ILP32: str x17, [x16, :tprel_lo12_nc:var] // encoding:
> [0x11,0bAAAAAA10,0b00AAAAAA,0xf9]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale8
> +
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12 [[VARSYM]]
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC [[VARSYM]]
> +
> +
> + ldr q24, [x23, :tprel_lo12:var]
> + str q22, [x21, :tprel_lo12_nc:var]
> +// CHECK-ILP32: ldr q24, [x23, :tprel_lo12:var] // encoding:
> [0xf8,0bAAAAAA10,0b11AAAAAA,0x3d]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale16
> +// CHECK-ILP32: str q22, [x21, :tprel_lo12_nc:var] // encoding:
> [0xb6,0bAAAAAA10,0b10AAAAAA,0x3d]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale16
> +
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12 [[VARSYM]]
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12_NC [[VARSYM]]
> +
>
> +////////////////////////////////////////////////////////////////////////////////
> +// TLS local-dynamic forms
>
> +////////////////////////////////////////////////////////////////////////////////
> +
> + movz x5, #:dtprel_g1:var
> + movn x6, #:dtprel_g1:var
> + movz w7, #:dtprel_g1:var
> +// CHECK-ILP32: movz x5, #:dtprel_g1:var // encoding:
> [0bAAA00101,A,0b101AAAAA,0x92]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw
> +// CHECK-ILP32: movn x6, #:dtprel_g1:var // encoding:
> [0bAAA00110,A,0b101AAAAA,0x92]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw
> +// CHECK-ILP32: movz w7, #:dtprel_g1:var // encoding:
> [0bAAA00111,A,0b101AAAAA,0x12]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw
> +
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLD_MOVW_DTPREL_G1 [[VARSYM]]
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLD_MOVW_DTPREL_G1 [[VARSYM]]
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLD_MOVW_DTPREL_G1 [[VARSYM]]
> +
> +
> + movz x11, #:dtprel_g0:var
> + movn x12, #:dtprel_g0:var
> + movz w13, #:dtprel_g0:var
> +// CHECK-ILP32: movz x11, #:dtprel_g0:var // encoding:
> [0bAAA01011,A,0b100AAAAA,0x92]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw
> +// CHECK-ILP32: movn x12, #:dtprel_g0:var // encoding:
> [0bAAA01100,A,0b100AAAAA,0x92]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw
> +// CHECK-ILP32: movz w13, #:dtprel_g0:var // encoding:
> [0bAAA01101,A,0b100AAAAA,0x12]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw
> +
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0 [[VARSYM]]
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0 [[VARSYM]]
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0 [[VARSYM]]
> +
> +
> + movk x15, #:dtprel_g0_nc:var
> + movk w16, #:dtprel_g0_nc:var
> +// CHECK-ILP32: movk x15, #:dtprel_g0_nc:var // encoding:
> [0bAAA01111,A,0b100AAAAA,0xf2]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :dtprel_g0_nc:var, kind: fixup_aarch64_movw
> +// CHECK-ILP32: movk w16, #:dtprel_g0_nc:var // encoding:
> [0bAAA10000,A,0b100AAAAA,0x72]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :dtprel_g0_nc:var, kind: fixup_aarch64_movw
> +
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]]
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]]
> +
> +
> + add x21, x22, #:dtprel_lo12:var
> +// CHECK-ILP32: add x21, x22, :dtprel_lo12:var // encoding:
> [0xd5,0bAAAAAA10,0b00AAAAAA,0x91]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_add_imm12
> +
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12 [[VARSYM]]
> +
> +
> + add x25, x26, #:dtprel_lo12_nc:var
> +// CHECK-ILP32: add x25, x26, :dtprel_lo12_nc:var // encoding:
> [0x59,0bAAAAAA11,0b00AAAAAA,0x91]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_add_imm12
> +
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12_NC [[VARSYM]]
> +
> +
> + add x0, x0, #:dtprel_hi12:var_tlsld, lsl #12
> + add x0, x0, #:tprel_hi12:var_tlsle, lsl #12
> +
> +// CHECK-ELF-ILP32: R_AARCH64_P32_TLSLD_ADD_DTPREL_HI12 var_tlsld
> +// CHECK-ELF-ILP32: R_AARCH64_P32_TLSLE_ADD_TPREL_HI12 var_tlsle
> +
> +
> + ldrb w29, [x30, #:dtprel_lo12:var]
> + ldrsb x29, [x28, #:dtprel_lo12_nc:var]
> +// CHECK-ILP32: ldrb w29, [x30, :dtprel_lo12:var] // encoding:
> [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale1
> +// CHECK-ILP32: ldrsb x29, [x28, :dtprel_lo12_nc:var] // encoding:
> [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale1
> +
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 [[VARSYM]]
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC [[VARSYM]]
> +
> +
> + strh w27, [x26, #:dtprel_lo12:var]
> + ldrsh x25, [x24, #:dtprel_lo12_nc:var]
> +// CHECK-ILP32: strh w27, [x26, :dtprel_lo12:var] // encoding:
> [0x5b,0bAAAAAA11,0b00AAAAAA,0x79]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale2
> +// CHECK-ILP32: ldrsh x25, [x24, :dtprel_lo12_nc:var] // encoding:
> [0x19,0bAAAAAA11,0b10AAAAAA,0x79]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale2
> +
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 [[VARSYM]]
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC [[VARSYM]]
> +
> +
> + ldr w23, [x22, #:dtprel_lo12:var]
> + ldrsw x21, [x20, #:dtprel_lo12_nc:var]
> +// CHECK-ILP32: ldr w23, [x22, :dtprel_lo12:var] // encoding:
> [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale4
> +// CHECK-ILP32: ldrsw x21, [x20, :dtprel_lo12_nc:var] // encoding:
> [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale4
> +
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12 [[VARSYM]]
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC [[VARSYM]]
> +
> + ldr x19, [x18, #:dtprel_lo12:var]
> + str x17, [x16, #:dtprel_lo12_nc:var]
> +// CHECK-ILP32: ldr x19, [x18, :dtprel_lo12:var] // encoding:
> [0x53,0bAAAAAA10,0b01AAAAAA,0xf9]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8
> +// CHECK-ILP32: str x17, [x16, :dtprel_lo12_nc:var] // encoding:
> [0x11,0bAAAAAA10,0b00AAAAAA,0xf9]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale8
> +
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12 [[VARSYM]]
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12_NC [[VARSYM]]
> +
> + ldr q24, [x23, #:dtprel_lo12:var]
> + str q22, [x21, #:dtprel_lo12_nc:var]
> +// CHECK-ILP32: ldr q24, [x23, :dtprel_lo12:var] // encoding:
> [0xf8,0bAAAAAA10,0b11AAAAAA,0x3d]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale16
> +// CHECK-ILP32: str q22, [x21, :dtprel_lo12_nc:var] // encoding:
> [0xb6,0bAAAAAA10,0b10AAAAAA,0x3d]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :dtprel_lo12_nc:var, kind:
> fixup_aarch64_ldst_imm12_scale16
> +
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12 [[VARSYM]]
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12_NC [[VARSYM]]
> +
>
> +////////////////////////////////////////////////////////////////////////////////
> +// TLS descriptor forms
>
> +////////////////////////////////////////////////////////////////////////////////
> +
> + adrp x8, :tlsdesc:var
> + ldr w7, [x6, #:tlsdesc_lo12:var]
> + add x5, x4, #:tlsdesc_lo12:var
> + .tlsdesccall var
> + blr x3
> +
> +// CHECK-ILP32: adrp x8, :tlsdesc:var // encoding:
> [0x08'A',A,A,0x90'A']
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :tlsdesc:var, kind: fixup_aarch64_pcrel_adrp_imm21
> +// CHECK-ILP32: ldr w7, [x6, :tlsdesc_lo12:var] // encoding:
> [0xc7,0bAAAAAA00,0b01AAAAAA,0xb9]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :tlsdesc_lo12:var, kind: fixup_aarch64_ldst_imm12_scale4
> +// CHECK-ILP32: add x5, x4, :tlsdesc_lo12:var // encoding:
> [0x85,0bAAAAAA00,0b00AAAAAA,0x91]
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: :tlsdesc_lo12:var, kind: fixup_aarch64_add_imm12
> +// CHECK-ILP32: .tlsdesccall var // encoding: []
> +// CHECK-ILP32-NEXT: // fixup A -
> offset: 0, value: var, kind: fixup_aarch64_tlsdesc_call
> +// CHECK-ILP32: blr x3 // encoding:
> [0x60,0x00,0x3f,0xd6]
> +
> +
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSDESC_ADR_PAGE21 [[VARSYM]]
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSDESC_LD32_LO12 [[VARSYM]]
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}}
> R_AARCH64_P32_TLSDESC_ADD_LO12 [[VARSYM]]
> +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSDESC_CALL
> [[VARSYM]]
> +
> + // Make sure symbol 5 has type STT_TLS:
> +
> +// CHECK-ELF-ILP32: Symbols [
> +// CHECK-ELF-ILP32: Symbol {
> +// CHECK-ELF-ILP32: Name: var
> +// CHECK-ELF-ILP32-NEXT: Value:
> +// CHECK-ELF-ILP32-NEXT: Size:
> +// CHECK-ELF-ILP32-NEXT: Binding: Global
> +// CHECK-ELF-ILP32-NEXT: Type: TLS
>
> Modified: llvm/trunk/test/MC/AArch64/arm64-elf-reloc-condbr.s
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-elf-reloc-condbr.s?rev=301939&r1=301938&r2=301939&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/MC/AArch64/arm64-elf-reloc-condbr.s (original)
> +++ llvm/trunk/test/MC/AArch64/arm64-elf-reloc-condbr.s Tue May 2
> 12:14:31 2017
> @@ -1,5 +1,8 @@
> // RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj %s -o - | \
> // RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s
> +// RUN: llvm-mc -target-abi=ilp32 -triple=arm64-none-linux-gnu
> -filetype=obj \
> +// RUN: %s -o - | \
> +// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ-ILP32 %s
>
> b.eq somewhere
>
> @@ -8,3 +11,9 @@
> // OBJ-NEXT: 0x0 R_AARCH64_CONDBR19 somewhere 0x0
> // OBJ-NEXT: }
> // OBJ-NEXT: ]
> +
> +// OBJ-ILP32: Relocations [
> +// OBJ-ILP32-NEXT: Section {{.*}} .rela.text {
> +// OBJ-ILP32-NEXT: 0x0 R_AARCH64_P32_CONDBR19 somewhere 0x0
> +// OBJ-ILP32-NEXT: }
> +// OBJ-ILP32-NEXT: ]
>
> Modified: llvm/trunk/test/MC/AArch64/arm64-elf-relocs.s
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-elf-relocs.s?rev=301939&r1=301938&r2=301939&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/MC/AArch64/arm64-elf-relocs.s (original)
> +++ llvm/trunk/test/MC/AArch64/arm64-elf-relocs.s Tue May 2 12:14:31 2017
> @@ -1,5 +1,7 @@
> // RUN: llvm-mc -triple=arm64-linux-gnu -o - < %s | FileCheck %s
> -// RUN: llvm-mc -triple=arm64-linux-gnu -filetype=obj <
> %s | \
> +// RUN: llvm-mc -triple=arm64-linux-gnu -show-encoding -o - < %s | \
> +// RUN: FileCheck --check-prefix=CHECK-ENCODING %s
> +// RUN: llvm-mc -triple=arm64-linux-gnu -filetype=obj < %s | \
> // RUN: llvm-objdump -triple=arm64-linux-gnu - -r | \
> // RUN: FileCheck %s --check-prefix=CHECK-OBJ-LP64
>
> @@ -25,7 +27,7 @@
>
> add x5, x0, #:tlsdesc_lo12:sym
> // CHECK: add x5, x0, :tlsdesc_lo12:sym
> -// CHECK-OBJ-LP64: 14 R_AARCH64_TLSDESC_ADD_LO12_NC sym
> +// CHECK-OBJ-LP64: 14 R_AARCH64_TLSDESC_ADD_LO12 sym
>
> add x0, x2, #:lo12:sym+8
> // CHECK: add x0, x2, :lo12:sym
> @@ -49,37 +51,37 @@
>
> add x5, x0, #:tlsdesc_lo12:sym+70
> // CHECK: add x5, x0, :tlsdesc_lo12:sym+70
> -// CHECK-OBJ-LP64: 2c R_AARCH64_TLSDESC_ADD_LO12_NC sym+70
> +// CHECK-OBJ-LP64: 2c R_AARCH64_TLSDESC_ADD_LO12 sym+70
>
> .hword sym + 4 - .
> // CHECK-OBJ-LP64: 30 R_AARCH64_PREL16 sym+4
> .word sym - . + 8
> -// CHECK-OBJ-LP64 32 R_AARCH64_PREL32 sym+8
> +// CHECK-OBJ-LP64: 32 R_AARCH64_PREL32 sym+8
> .xword sym-.
> -// CHECK-OBJ-LP64 36 R_AARCH64_PREL64 sym{{$}}
> +// CHECK-OBJ-LP64: 36 R_AARCH64_PREL64 sym{{$}}
>
> .hword sym
> -// CHECK-OBJ-LP64 3e R_AARCH64_ABS16 sym
> +// CHECK-OBJ-LP64: 3e R_AARCH64_ABS16 sym
> .word sym+1
> -// CHECK-OBJ-LP64 40 R_AARCH64_ABS32 sym+1
> +// CHECK-OBJ-LP64: 40 R_AARCH64_ABS32 sym+1
> .xword sym+16
> -// CHECK-OBJ-LP64 44 R_AARCH64_ABS64 sym+16
> +// CHECK-OBJ-LP64: 44 R_AARCH64_ABS64 sym+16
>
> adrp x0, sym
> // CHECK: adrp x0, sym
> -// CHECK-OBJ-LP64 4c R_AARCH64_ADR_PREL_PG_HI21 sym
> +// CHECK-OBJ-LP64: 4c R_AARCH64_ADR_PREL_PG_HI21 sym
>
> adrp x15, :got:sym
> // CHECK: adrp x15, :got:sym
> -// CHECK-OBJ-LP64 50 R_AARCH64_ADR_GOT_PAGE sym
> +// CHECK-OBJ-LP64: 50 R_AARCH64_ADR_GOT_PAGE sym
>
> adrp x29, :gottprel:sym
> // CHECK: adrp x29, :gottprel:sym
> -// CHECK-OBJ-LP64 54 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 sym
> +// CHECK-OBJ-LP64: 54 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 sym
>
> adrp x2, :tlsdesc:sym
> // CHECK: adrp x2, :tlsdesc:sym
> -// CHECK-OBJ-LP64 58 R_AARCH64_TLSDESC_ADR_PAGE21 sym
> +// CHECK-OBJ-LP64: 58 R_AARCH64_TLSDESC_ADR_PAGE21 sym
>
> // LLVM is not competent enough to do this relocation because the
> // page boundary could occur anywhere after linking. A relocation
> @@ -88,7 +90,7 @@
> .global trickQuestion
> trickQuestion:
> // CHECK: adrp x3, trickQuestion
> -// CHECK-OBJ-LP64 5c R_AARCH64_ADR_PREL_PG_HI21 trickQuestion
> +// CHECK-OBJ-LP64: 5c R_AARCH64_ADR_PREL_PG_HI21 trickQuestion
>
> ldrb w2, [x3, :lo12:sym]
> ldrsb w5, [x7, #:lo12:sym]
> @@ -98,10 +100,10 @@ trickQuestion:
> // CHECK: ldrsb w5, [x7, :lo12:sym]
> // CHECK: ldrsb x11, [x13, :lo12:sym]
> // CHECK: ldr b17, [x19, :lo12:sym]
> -// CHECK-OBJ-LP64 R_AARCH64_LDST8_ABS_LO12_NC sym
> -// CHECK-OBJ-LP64 R_AARCH64_LDST8_ABS_LO12_NC sym
> -// CHECK-OBJ-LP64 R_AARCH64_LDST8_ABS_LO12_NC sym
> -// CHECK-OBJ-LP64 R_AARCH64_LDST8_ABS_LO12_NC sym
> +// CHECK-OBJ-LP64: R_AARCH64_LDST8_ABS_LO12_NC sym
> +// CHECK-OBJ-LP64: R_AARCH64_LDST8_ABS_LO12_NC sym
> +// CHECK-OBJ-LP64: R_AARCH64_LDST8_ABS_LO12_NC sym
> +// CHECK-OBJ-LP64: R_AARCH64_LDST8_ABS_LO12_NC sym
>
> ldrb w23, [x29, #:dtprel_lo12_nc:sym]
> ldrsb w23, [x19, #:dtprel_lo12:sym]
> @@ -111,10 +113,10 @@ trickQuestion:
> // CHECK: ldrsb w23, [x19, :dtprel_lo12:sym]
> // CHECK: ldrsb x17, [x13, :dtprel_lo12_nc:sym]
> // CHECK: ldr b11, [x7, :dtprel_lo12:sym]
> -// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym
> -// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym
> -// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym
> -// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym
> +// CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym
> +// CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym
> +// CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym
> +// CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym
>
> ldrb w1, [x2, :tprel_lo12:sym]
> ldrsb w3, [x4, #:tprel_lo12_nc:sym]
> @@ -124,10 +126,10 @@ trickQuestion:
> // CHECK: ldrsb w3, [x4, :tprel_lo12_nc:sym]
> // CHECK: ldrsb x5, [x6, :tprel_lo12:sym]
> // CHECK: ldr b7, [x8, :tprel_lo12_nc:sym]
> -// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym
> -// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym
> -// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym
> -// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym
> +// CHECK-OBJ-LP64: R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym
> +// CHECK-OBJ-LP64: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym
> +// CHECK-OBJ-LP64: R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym
> +// CHECK-OBJ-LP64: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym
>
> ldrh w2, [x3, #:lo12:sym]
> ldrsh w5, [x7, :lo12:sym]
> @@ -137,10 +139,10 @@ trickQuestion:
> // CHECK: ldrsh w5, [x7, :lo12:sym]
> // CHECK: ldrsh x11, [x13, :lo12:sym]
> // CHECK: ldr h17, [x19, :lo12:sym]
> -// CHECK-OBJ-LP64 R_AARCH64_LDST16_ABS_LO12_NC sym
> -// CHECK-OBJ-LP64 R_AARCH64_LDST16_ABS_LO12_NC sym
> -// CHECK-OBJ-LP64 R_AARCH64_LDST16_ABS_LO12_NC sym
> -// CHECK-OBJ-LP64 R_AARCH64_LDST16_ABS_LO12_NC sym
> +// CHECK-OBJ-LP64: R_AARCH64_LDST16_ABS_LO12_NC sym
> +// CHECK-OBJ-LP64: R_AARCH64_LDST16_ABS_LO12_NC sym
> +// CHECK-OBJ-LP64: R_AARCH64_LDST16_ABS_LO12_NC sym
> +// CHECK-OBJ-LP64: R_AARCH64_LDST16_ABS_LO12_NC sym
>
> ldrh w23, [x29, #:dtprel_lo12_nc:sym]
> ldrsh w23, [x19, :dtprel_lo12:sym]
> @@ -150,10 +152,10 @@ trickQuestion:
> // CHECK: ldrsh w23, [x19, :dtprel_lo12:sym]
> // CHECK: ldrsh x17, [x13, :dtprel_lo12_nc:sym]
> // CHECK: ldr h11, [x7, :dtprel_lo12:sym]
> -// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym
> -// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym
> -// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym
> -// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym
> +// CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym
> +// CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym
> +// CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym
> +// CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym
>
> ldrh w1, [x2, :tprel_lo12:sym]
> ldrsh w3, [x4, #:tprel_lo12_nc:sym]
> @@ -163,10 +165,10 @@ trickQuestion:
> // CHECK: ldrsh w3, [x4, :tprel_lo12_nc:sym]
> // CHECK: ldrsh x5, [x6, :tprel_lo12:sym]
> // CHECK: ldr h7, [x8, :tprel_lo12_nc:sym]
> -// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym
> -// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym
> -// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym
> -// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym
> +// CHECK-OBJ-LP64: R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym
> +// CHECK-OBJ-LP64: R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym
> +// CHECK-OBJ-LP64: R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym
> +// CHECK-OBJ-LP64: R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym
>
> ldr w1, [x2, #:lo12:sym]
> ldrsw x3, [x4, #:lo12:sym]
> @@ -174,9 +176,9 @@ trickQuestion:
> // CHECK: ldr w1, [x2, :lo12:sym]
> // CHECK: ldrsw x3, [x4, :lo12:sym]
> // CHECK: ldr s4, [x5, :lo12:sym]
> -// CHECK-OBJ-LP64 R_AARCH64_LDST32_ABS_LO12_NC sym
> -// CHECK-OBJ-LP64 R_AARCH64_LDST32_ABS_LO12_NC sym
> -// CHECK-OBJ-LP64 R_AARCH64_LDST32_ABS_LO12_NC sym
> +// CHECK-OBJ-LP64: R_AARCH64_LDST32_ABS_LO12_NC sym
> +// CHECK-OBJ-LP64: R_AARCH64_LDST32_ABS_LO12_NC sym
> +// CHECK-OBJ-LP64: R_AARCH64_LDST32_ABS_LO12_NC sym
>
> ldr w1, [x2, :dtprel_lo12:sym]
> ldrsw x3, [x4, #:dtprel_lo12_nc:sym]
> @@ -184,9 +186,9 @@ trickQuestion:
> // CHECK: ldr w1, [x2, :dtprel_lo12:sym]
> // CHECK: ldrsw x3, [x4, :dtprel_lo12_nc:sym]
> // CHECK: ldr s4, [x5, :dtprel_lo12_nc:sym]
> -// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST32_DTPREL_LO12 sym
> -// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym
> -// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym
> +// CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST32_DTPREL_LO12 sym
> +// CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym
> +// CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym
>
>
> ldr w1, [x2, #:tprel_lo12:sym]
> @@ -195,55 +197,73 @@ trickQuestion:
> // CHECK: ldr w1, [x2, :tprel_lo12:sym]
> // CHECK: ldrsw x3, [x4, :tprel_lo12_nc:sym]
> // CHECK: ldr s4, [x5, :tprel_lo12_nc:sym]
>
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