<div dir="ltr">Hi Joel,<div><br></div><div>I had to revert this because it was breaking compilation.</div><div><br></div><div>Example errors:</div><div><br></div><div><div>D:\src\llvm-mono\lld\ELF\Target.cpp(1379): note: see usage of 'R_AARCH64_TLSDESC_ADD_LO12_NC'</div><div>D:\src\llvm-mono\lld\ELF\Target.cpp(1380): error C2065: 'R_AARCH64_TLSDESC_LD64_LO12_NC': undeclared identifier</div><div>D:\src\llvm-mono\lld\ELF\Target.cpp(1380): error C2131: expression did not evaluate to a constant</div><div>D:\src\llvm-mono\lld\ELF\Target.cpp(1380): note: failure was caused by non-constant arguments or reference to a non-constant symbol</div><div>D:\src\llvm-mono\lld\ELF\Target.cpp(1380): note: see usage of 'R_AARCH64_TLSDESC_LD64_LO12_NC'</div><div>D:\src\llvm-mono\lld\ELF\Target.cpp(1379): error C2051: case expression not constant</div><div>D:\src\llvm-mono\lld\ELF\Target.cpp(1380): error C2051: case expression not constant</div><div>D:\src\llvm-mono\lld\ELF\Target.cpp(1506): error C2065: 'R_AARCH64_TLSDESC_LD64_LO12_NC': undeclared identifier</div><div>D:\src\llvm-mono\lld\ELF\Target.cpp(1506): error C2131: expression did not evaluate to a constant</div><div>D:\src\llvm-mono\lld\ELF\Target.cpp(1506): note: failure was caused by non-constant arguments or reference to a non-constant symbol</div><div>D:\src\llvm-mono\lld\ELF\Target.cpp(1506): note: see usage of 'R_AARCH64_TLSDESC_LD64_LO12_NC'</div><div>D:\src\llvm-mono\lld\ELF\Target.cpp(1546): error C2065: 'R_AARCH64_TLSDESC_ADD_LO12_NC': undeclared identifier</div><div>D:\src\llvm-mono\lld\ELF\Target.cpp(1546): error C2131: expression did not evaluate to a constant</div><div>D:\src\llvm-mono\lld\ELF\Target.cpp(1546): note: failure was caused by non-constant arguments or reference to a non-constant symbol</div><div>D:\src\llvm-mono\lld\ELF\Target.cpp(1546): note: see usage of 'R_AARCH64_TLSDESC_ADD_LO12_NC'</div><div>D:\src\llvm-mono\lld\ELF\Target.cpp(1506): error C2051: case expression not constant</div><div>D:\src\llvm-mono\lld\ELF\Target.cpp(1546): error C2051: case expression not constant</div><div>D:\src\llvm-mono\lld\ELF\Target.cpp(1570): error C2065: 'R_AARCH64_TLSDESC_ADD_LO12_NC': undeclared identifier</div><div>D:\src\llvm-mono\lld\ELF\Target.cpp(1570): error C2131: expression did not evaluate to a constant</div><div>D:\src\llvm-mono\lld\ELF\Target.cpp(1570): note: failure was caused by non-constant arguments or reference to a non-c</div></div><div><br></div><div>But there were many more as well. Please resubmit after fixing these up.</div></div><br><div class="gmail_quote"><div dir="ltr">On Tue, May 2, 2017 at 10:27 AM Joel Jones via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: joel_k_jones<br>
Date: Tue May 2 12:14:31 2017<br>
New Revision: 301939<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=301939&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=301939&view=rev</a><br>
Log:<br>
Remove "_NC" suffix and semantics from TLSDESC_LD{64,32}_LO12 and<br>
TLSDESC_ADD_LO12 relocations<br>
Rearrange ordering in AArch64.def to follow relocation encoding<br>
Fix name:<br>
R_AARCH64_P32_LD64_GOT_LO12_NC => R_AARCH64_P32_LD32_GOT_LO12_NC<br>
Add support for several "TLS", "TLSGD", and "TLSLD" relocations for<br>
ILP32<br>
Fix return values from isNonILP32reloc<br>
Add implementations for<br>
R_AARCH64_ADR_PREL_PG_HI21_NC, R_AARCH64_P32_LD32_GOT_LO12_NC,<br>
R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC,<br>
R_AARCH64_P32_TLSDESC_LD32_LO12, R_AARCH64_LD64_GOT_LO12_NC,<br>
*TLSLD_LDST128_DTPREL_LO12, *TLSLD_LDST128_DTPREL_LO12_NC,<br>
*TLSLE_LDST128_TPREL_LO12, *TLSLE_LDST128_TPREL_LO12_NC<br>
Modify error messages to give name of equivalent relocation in the<br>
ABI not being used, along with better checking for non-existent<br>
requested relocations.<br>
Added assembler support for "pg_hi21_nc"<br>
Relocation definitions added without implementations:<br>
R_AARCH64_P32_TLSDESC_ADR_PREL21, R_AARCH64_P32_TLSGD_ADR_PREL21,<br>
R_AARCH64_P32_TLSGD_ADD_LO12_NC, R_AARCH64_P32_TLSLD_ADR_PREL21,<br>
R_AARCH64_P32_TLSLD_ADR_PAGE21, R_AARCH64_P32_TLSLD_ADD_LO12_NC,<br>
R_AARCH64_P32_TLSLD_LD_PREL19, R_AARCH64_P32_TLSDESC_LD_PREL19,<br>
R_AARCH64_P32_TLSGD_ADR_PAGE21, R_AARCH64_P32_TLS_DTPREL,<br>
R_AARCH64_P32_TLS_DTPMOD, R_AARCH64_P32_TLS_TPREL,<br>
R_AARCH64_P32_TLSDESC<br>
Fix encoding:<br>
R_AARCH64_P32_TLSDESC_ADR_PAGE21<br>
<br>
Reviewers: Peter Smith<br>
<br>
Patch by: Joel Jones (<a href="mailto:jjones@cavium.com" target="_blank">jjones@cavium.com</a>)<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D32072" rel="noreferrer" target="_blank">https://reviews.llvm.org/D32072</a><br>
<br>
Added:<br>
llvm/trunk/test/MC/AArch64/arm32-large-relocs.s<br>
llvm/trunk/test/MC/AArch64/arm32-tls-relocs.s<br>
llvm/trunk/test/MC/AArch64/elf-reloc-pcreladdressing-ilp32.s<br>
llvm/trunk/test/MC/AArch64/lp64-diagnostics.s<br>
Modified:<br>
llvm/trunk/include/llvm/Support/ELFRelocs/AArch64.def<br>
llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp<br>
llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp<br>
llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.cpp<br>
llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h<br>
llvm/trunk/test/CodeGen/AArch64/arm64-tls-dynamics.ll<br>
llvm/trunk/test/MC/AArch64/adrp-relocation.s<br>
llvm/trunk/test/MC/AArch64/arm32-elf-relocs.s<br>
llvm/trunk/test/MC/AArch64/arm64-elf-reloc-condbr.s<br>
llvm/trunk/test/MC/AArch64/arm64-elf-relocs.s<br>
llvm/trunk/test/MC/AArch64/arm64-tls-relocs.s<br>
llvm/trunk/test/MC/AArch64/elf-reloc-ldrlit.s<br>
llvm/trunk/test/MC/AArch64/elf-reloc-tstb.s<br>
llvm/trunk/test/MC/AArch64/elf-reloc-uncondbrimm.s<br>
llvm/trunk/test/MC/AArch64/error-location.s<br>
llvm/trunk/test/MC/AArch64/ilp32-diagnostics.s<br>
llvm/trunk/test/MC/AArch64/inline-asm-modifiers.s<br>
llvm/trunk/test/MC/AArch64/tls-relocs.s<br>
llvm/trunk/test/tools/llvm-readobj/reloc-types.test<br>
<br>
Modified: llvm/trunk/include/llvm/Support/ELFRelocs/AArch64.def<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ELFRelocs/AArch64.def?rev=301939&r1=301938&r2=301939&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ELFRelocs/AArch64.def?rev=301939&r1=301938&r2=301939&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/Support/ELFRelocs/AArch64.def (original)<br>
+++ llvm/trunk/include/llvm/Support/ELFRelocs/AArch64.def Tue May 2 12:14:31 2017<br>
@@ -109,8 +109,8 @@ ELF_RELOC(R_AARCH64_TLSLE_LDST64_TPREL_L<br>
ELF_RELOC(R_AARCH64_TLSDESC_LD_PREL19, 0x230)<br>
ELF_RELOC(R_AARCH64_TLSDESC_ADR_PREL21, 0x231)<br>
ELF_RELOC(R_AARCH64_TLSDESC_ADR_PAGE21, 0x232)<br>
-ELF_RELOC(R_AARCH64_TLSDESC_LD64_LO12_NC, 0x233)<br>
-ELF_RELOC(R_AARCH64_TLSDESC_ADD_LO12_NC, 0x234)<br>
+ELF_RELOC(R_AARCH64_TLSDESC_LD64_LO12, 0x233)<br>
+ELF_RELOC(R_AARCH64_TLSDESC_ADD_LO12, 0x234)<br>
ELF_RELOC(R_AARCH64_TLSDESC_OFF_G1, 0x235)<br>
ELF_RELOC(R_AARCH64_TLSDESC_OFF_G0_NC, 0x236)<br>
ELF_RELOC(R_AARCH64_TLSDESC_LDR, 0x237)<br>
@@ -144,21 +144,28 @@ ELF_RELOC(R_AARCH64_P32_ADR_PREL_LO21,<br>
ELF_RELOC(R_AARCH64_P32_ADR_PREL_PG_HI21, 0x00b)<br>
ELF_RELOC(R_AARCH64_P32_ADD_ABS_LO12_NC, 0x00c)<br>
ELF_RELOC(R_AARCH64_P32_LDST8_ABS_LO12_NC, 0x00d)<br>
+ELF_RELOC(R_AARCH64_P32_LDST16_ABS_LO12_NC, 0x00e)<br>
+ELF_RELOC(R_AARCH64_P32_LDST32_ABS_LO12_NC, 0x00f)<br>
+ELF_RELOC(R_AARCH64_P32_LDST64_ABS_LO12_NC, 0x010)<br>
+ELF_RELOC(R_AARCH64_P32_LDST128_ABS_LO12_NC, 0x011)<br>
ELF_RELOC(R_AARCH64_P32_TSTBR14, 0x012)<br>
ELF_RELOC(R_AARCH64_P32_CONDBR19, 0x013)<br>
ELF_RELOC(R_AARCH64_P32_JUMP26, 0x014)<br>
ELF_RELOC(R_AARCH64_P32_CALL26, 0x015)<br>
-ELF_RELOC(R_AARCH64_P32_LDST16_ABS_LO12_NC, 0x00e)<br>
-ELF_RELOC(R_AARCH64_P32_LDST32_ABS_LO12_NC, 0x00f)<br>
-ELF_RELOC(R_AARCH64_P32_LDST64_ABS_LO12_NC, 0x010)<br>
ELF_RELOC(R_AARCH64_P32_MOVW_PREL_G0, 0x016)<br>
ELF_RELOC(R_AARCH64_P32_MOVW_PREL_G0_NC, 0x017)<br>
ELF_RELOC(R_AARCH64_P32_MOVW_PREL_G1, 0x018)<br>
-ELF_RELOC(R_AARCH64_P32_LDST128_ABS_LO12_NC, 0x011)<br>
ELF_RELOC(R_AARCH64_P32_GOT_LD_PREL19, 0x019)<br>
ELF_RELOC(R_AARCH64_P32_ADR_GOT_PAGE, 0x01a)<br>
-ELF_RELOC(R_AARCH64_P32_LD64_GOT_LO12_NC, 0x01b)<br>
+ELF_RELOC(R_AARCH64_P32_LD32_GOT_LO12_NC, 0x01b)<br>
ELF_RELOC(R_AARCH64_P32_LD32_GOTPAGE_LO14, 0x01c)<br>
+ELF_RELOC(R_AARCH64_P32_TLSGD_ADR_PREL21, 0x050)<br>
+ELF_RELOC(R_AARCH64_P32_TLSGD_ADR_PAGE21, 0x051)<br>
+ELF_RELOC(R_AARCH64_P32_TLSGD_ADD_LO12_NC, 0x052)<br>
+ELF_RELOC(R_AARCH64_P32_TLSLD_ADR_PREL21, 0x053)<br>
+ELF_RELOC(R_AARCH64_P32_TLSLD_ADR_PAGE21, 0x054)<br>
+ELF_RELOC(R_AARCH64_P32_TLSLD_ADD_LO12_NC, 0x055)<br>
+ELF_RELOC(R_AARCH64_P32_TLSLD_LD_PREL19, 0x056)<br>
ELF_RELOC(R_AARCH64_P32_TLSLD_MOVW_DTPREL_G1, 0x057)<br>
ELF_RELOC(R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0, 0x058)<br>
ELF_RELOC(R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0_NC, 0x059)<br>
@@ -173,6 +180,8 @@ ELF_RELOC(R_AARCH64_P32_TLSLD_LDST32_DTP<br>
ELF_RELOC(R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC, 0x062)<br>
ELF_RELOC(R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12, 0x063)<br>
ELF_RELOC(R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12_NC, 0x064)<br>
+ELF_RELOC(R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12, 0x065)<br>
+ELF_RELOC(R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12_NC,0x066)<br>
ELF_RELOC(R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21, 0x067)<br>
ELF_RELOC(R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC, 0x068)<br>
ELF_RELOC(R_AARCH64_P32_TLSIE_LD_GOTTPREL_PREL19, 0x069)<br>
@@ -190,12 +199,20 @@ ELF_RELOC(R_AARCH64_P32_TLSLE_LDST32_TPR<br>
ELF_RELOC(R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC, 0x075)<br>
ELF_RELOC(R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12, 0x076)<br>
ELF_RELOC(R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC, 0x077)<br>
-ELF_RELOC(R_AARCH64_P32_TLSDESC_ADR_PAGE21, 0x051)<br>
-ELF_RELOC(R_AARCH64_P32_TLSDESC_LD32_LO12_NC, 0x07d)<br>
-ELF_RELOC(R_AARCH64_P32_TLSDESC_ADD_LO12_NC, 0x034)<br>
+ELF_RELOC(R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12, 0x078)<br>
+ELF_RELOC(R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12_NC, 0x079)<br>
+ELF_RELOC(R_AARCH64_P32_TLSDESC_LD_PREL19, 0x07a)<br>
+ELF_RELOC(R_AARCH64_P32_TLSDESC_ADR_PREL21, 0x07b)<br>
+ELF_RELOC(R_AARCH64_P32_TLSDESC_ADR_PAGE21, 0x07c)<br>
+ELF_RELOC(R_AARCH64_P32_TLSDESC_LD32_LO12, 0x07d)<br>
+ELF_RELOC(R_AARCH64_P32_TLSDESC_ADD_LO12, 0x07e)<br>
ELF_RELOC(R_AARCH64_P32_TLSDESC_CALL, 0x07f)<br>
ELF_RELOC(R_AARCH64_P32_COPY, 0x0b4)<br>
ELF_RELOC(R_AARCH64_P32_GLOB_DAT, 0x0b5)<br>
ELF_RELOC(R_AARCH64_P32_JUMP_SLOT, 0x0b6)<br>
ELF_RELOC(R_AARCH64_P32_RELATIVE, 0x0b7)<br>
+ELF_RELOC(R_AARCH64_P32_TLS_DTPREL, 0x0b8)<br>
+ELF_RELOC(R_AARCH64_P32_TLS_DTPMOD, 0x0b9)<br>
+ELF_RELOC(R_AARCH64_P32_TLS_TPREL, 0x0ba)<br>
+ELF_RELOC(R_AARCH64_P32_TLSDESC, 0x0bb)<br>
ELF_RELOC(R_AARCH64_P32_IRELATIVE, 0x0bc)<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp?rev=301939&r1=301938&r2=301939&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp?rev=301939&r1=301938&r2=301939&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp Tue May 2 12:14:31 2017<br>
@@ -580,8 +580,7 @@ void AArch64AsmPrinter::EmitInstruction(<br>
const MachineOperand &MO_Sym = MI->getOperand(0);<br>
MachineOperand MO_TLSDESC_LO12(MO_Sym), MO_TLSDESC(MO_Sym);<br>
MCOperand Sym, SymTLSDescLo12, SymTLSDesc;<br>
- MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGEOFF |<br>
- AArch64II::MO_NC);<br>
+ MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGEOFF);<br>
MO_TLSDESC.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGE);<br>
MCInstLowering.lowerOperand(MO_Sym, Sym);<br>
MCInstLowering.lowerOperand(MO_TLSDESC_LO12, SymTLSDescLo12);<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp?rev=301939&r1=301938&r2=301939&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp?rev=301939&r1=301938&r2=301939&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp Tue May 2 12:14:31 2017<br>
@@ -69,34 +69,34 @@ static bool isNonILP32reloc(const MCFixu<br>
return true;<br>
case AArch64MCExpr::VK_ABS_G2_S:<br>
Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G2));<br>
- return ELF::R_AARCH64_NONE;<br>
+ return true;<br>
case AArch64MCExpr::VK_ABS_G2_NC:<br>
Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2_NC));<br>
- return ELF::R_AARCH64_NONE;<br>
+ return true;<br>
case AArch64MCExpr::VK_ABS_G1_S:<br>
Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G1));<br>
- return ELF::R_AARCH64_NONE;<br>
+ return true;<br>
case AArch64MCExpr::VK_ABS_G1_NC:<br>
Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G1_NC));<br>
- return ELF::R_AARCH64_NONE;<br>
+ return true;<br>
case AArch64MCExpr::VK_DTPREL_G2:<br>
Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G2));<br>
- return ELF::R_AARCH64_NONE;<br>
+ return true;<br>
case AArch64MCExpr::VK_DTPREL_G1_NC:<br>
Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G1_NC));<br>
- return ELF::R_AARCH64_NONE;<br>
+ return true;<br>
case AArch64MCExpr::VK_TPREL_G2:<br>
Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G2));<br>
- return ELF::R_AARCH64_NONE;<br>
+ return true;<br>
case AArch64MCExpr::VK_TPREL_G1_NC:<br>
Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G1_NC));<br>
- return ELF::R_AARCH64_NONE;<br>
+ return true;<br>
case AArch64MCExpr::VK_GOTTPREL_G1:<br>
Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G1));<br>
- return ELF::R_AARCH64_NONE;<br>
+ return true;<br>
case AArch64MCExpr::VK_GOTTPREL_G0_NC:<br>
Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G0_NC));<br>
- return ELF::R_AARCH64_NONE;<br>
+ return true;<br>
default: return false;<br>
}<br>
return false;<br>
@@ -141,6 +141,16 @@ unsigned AArch64ELFObjectWriter::getRelo<br>
case AArch64::fixup_aarch64_pcrel_adrp_imm21:<br>
if (SymLoc == AArch64MCExpr::VK_ABS && !IsNC)<br>
return R_CLS(ADR_PREL_PG_HI21);<br>
+ if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) {<br>
+ if (IsILP32) {<br>
+ Ctx.reportError(Fixup.getLoc(),<br>
+ "invalid fixup for 32-bit pcrel ADRP instruction "<br>
+ "VK_ABS VK_NC");<br>
+ return ELF::R_AARCH64_NONE;<br>
+ } else {<br>
+ return ELF::R_AARCH64_ADR_PREL_PG_HI21_NC;<br>
+ }<br>
+ }<br>
if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC)<br>
return R_CLS(ADR_GOT_PAGE);<br>
if (SymLoc == AArch64MCExpr::VK_GOTTPREL && !IsNC)<br>
@@ -179,7 +189,8 @@ unsigned AArch64ELFObjectWriter::getRelo<br>
return R_CLS(ABS32);<br>
case FK_Data_8:<br>
if (IsILP32) {<br>
- Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(ABS64));<br>
+ Ctx.reportError(Fixup.getLoc(), "ILP32 8 byte absolute data "<br>
+ "relocation not supported (LP64 eqv: ABS64)");<br>
return ELF::R_AARCH64_NONE;<br>
} else<br>
return ELF::R_AARCH64_ABS64;<br>
@@ -197,7 +208,7 @@ unsigned AArch64ELFObjectWriter::getRelo<br>
if (RefKind == AArch64MCExpr::VK_TPREL_LO12)<br>
return R_CLS(TLSLE_ADD_TPREL_LO12);<br>
if (RefKind == AArch64MCExpr::VK_TLSDESC_LO12)<br>
- return R_CLS(TLSDESC_ADD_LO12_NC);<br>
+ return R_CLS(TLSDESC_ADD_LO12);<br>
if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)<br>
return R_CLS(ADD_ABS_LO12_NC);<br>
<br>
@@ -245,15 +256,67 @@ unsigned AArch64ELFObjectWriter::getRelo<br>
return R_CLS(TLSLE_LDST32_TPREL_LO12);<br>
if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)<br>
return R_CLS(TLSLE_LDST32_TPREL_LO12_NC);<br>
+ if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) {<br>
+ if (IsILP32) {<br>
+ return ELF::R_AARCH64_P32_LD32_GOT_LO12_NC;<br>
+ } else {<br>
+ Ctx.reportError(Fixup.getLoc(),<br>
+ "LP64 4 byte unchecked GOT load/store relocation "<br>
+ "not supported (ILP32 eqv: LD32_GOT_LO12_NC");<br>
+ return ELF::R_AARCH64_NONE;<br>
+ }<br>
+ }<br>
+ if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC) {<br>
+ if (IsILP32) {<br>
+ Ctx.reportError(Fixup.getLoc(),<br>
+ "ILP32 4 byte checked GOT load/store relocation "<br>
+ "not supported (unchecked eqv: LD32_GOT_LO12_NC)");<br>
+ } else {<br>
+ Ctx.reportError(Fixup.getLoc(),<br>
+ "LP64 4 byte checked GOT load/store relocation "<br>
+ "not supported (unchecked/ILP32 eqv: "<br>
+ "LD32_GOT_LO12_NC)");<br>
+ }<br>
+ return ELF::R_AARCH64_NONE;<br>
+ }<br>
+ if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) {<br>
+ if (IsILP32) {<br>
+ return ELF::R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC;<br>
+ } else {<br>
+ Ctx.reportError(Fixup.getLoc(), "LP64 32-bit load/store "<br>
+ "relocation not supported (ILP32 eqv: "<br>
+ "TLSIE_LD32_GOTTPREL_LO12_NC)");<br>
+ return ELF::R_AARCH64_NONE;<br>
+ }<br>
+ }<br>
+ if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC) {<br>
+ if (IsILP32) {<br>
+ return ELF::R_AARCH64_P32_TLSDESC_LD32_LO12;<br>
+ } else {<br>
+ Ctx.reportError(Fixup.getLoc(),<br>
+ "LP64 4 byte TLSDESC load/store relocation "<br>
+ "not supported (ILP32 eqv: TLSDESC_LD64_LO12)");<br>
+ return ELF::R_AARCH64_NONE;<br>
+ }<br>
+ }<br>
<br>
Ctx.reportError(Fixup.getLoc(),<br>
- "invalid fixup for 32-bit load/store instruction");<br>
+ "invalid fixup for 32-bit load/store instruction "<br>
+ "fixup_aarch64_ldst_imm12_scale4");<br>
return ELF::R_AARCH64_NONE;<br>
case AArch64::fixup_aarch64_ldst_imm12_scale8:<br>
if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)<br>
return R_CLS(LDST64_ABS_LO12_NC);<br>
- if (SymLoc == AArch64MCExpr::VK_GOT && IsNC)<br>
- return R_CLS(LD64_GOT_LO12_NC);<br>
+ if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) {<br>
+ if (!IsILP32) {<br>
+ return ELF::R_AARCH64_LD64_GOT_LO12_NC;<br>
+ } else {<br>
+ Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "<br>
+ "relocation not supported (LP64 eqv: "<br>
+ "LD64_GOT_LO12_NC)");<br>
+ return ELF::R_AARCH64_NONE;<br>
+ }<br>
+ }<br>
if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)<br>
return R_CLS(TLSLD_LDST64_DTPREL_LO12);<br>
if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)<br>
@@ -262,19 +325,40 @@ unsigned AArch64ELFObjectWriter::getRelo<br>
return R_CLS(TLSLE_LDST64_TPREL_LO12);<br>
if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)<br>
return R_CLS(TLSLE_LDST64_TPREL_LO12_NC);<br>
- if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC)<br>
- return IsILP32 ? ELF::R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC<br>
- : ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;<br>
- if (SymLoc == AArch64MCExpr::VK_TLSDESC && IsNC)<br>
- return IsILP32 ? ELF::R_AARCH64_P32_TLSDESC_LD32_LO12_NC<br>
- : ELF::R_AARCH64_TLSDESC_LD64_LO12_NC;<br>
-<br>
+ if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) {<br>
+ if (!IsILP32) {<br>
+ return ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;<br>
+ } else {<br>
+ Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "<br>
+ "relocation not supported (LP64 eqv: "<br>
+ "TLSIE_LD64_GOTTPREL_LO12_NC)");<br>
+ return ELF::R_AARCH64_NONE;<br>
+ }<br>
+ }<br>
+ if (SymLoc == AArch64MCExpr::VK_TLSDESC) {<br>
+ if (!IsILP32) {<br>
+ return ELF::R_AARCH64_TLSDESC_LD64_LO12;<br>
+ } else {<br>
+ Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "<br>
+ "relocation not supported (LP64 eqv: "<br>
+ "TLSDESC_LD64_LO12)");<br>
+ return ELF::R_AARCH64_NONE;<br>
+ }<br>
+ }<br>
Ctx.reportError(Fixup.getLoc(),<br>
"invalid fixup for 64-bit load/store instruction");<br>
return ELF::R_AARCH64_NONE;<br>
case AArch64::fixup_aarch64_ldst_imm12_scale16:<br>
if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)<br>
return R_CLS(LDST128_ABS_LO12_NC);<br>
+ if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)<br>
+ return R_CLS(TLSLD_LDST128_DTPREL_LO12);<br>
+ if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)<br>
+ return R_CLS(TLSLD_LDST128_DTPREL_LO12_NC);<br>
+ if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)<br>
+ return R_CLS(TLSLE_LDST128_TPREL_LO12);<br>
+ if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)<br>
+ return R_CLS(TLSLE_LDST128_TPREL_LO12_NC);<br>
<br>
Ctx.reportError(Fixup.getLoc(),<br>
"invalid fixup for 128-bit load/store instruction");<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.cpp?rev=301939&r1=301938&r2=301939&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.cpp?rev=301939&r1=301938&r2=301939&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.cpp Tue May 2 12:14:31 2017<br>
@@ -62,6 +62,7 @@ StringRef AArch64MCExpr::getVariantKindN<br>
case VK_TPREL_LO12_NC: return ":tprel_lo12_nc:";<br>
case VK_TLSDESC_LO12: return ":tlsdesc_lo12:";<br>
case VK_ABS_PAGE: return "";<br>
+ case VK_ABS_PAGE_NC: return ":pg_hi21_nc:";<br>
case VK_GOT_PAGE: return ":got:";<br>
case VK_GOT_LO12: return ":got_lo12:";<br>
case VK_GOTTPREL_PAGE: return ":gottprel:";<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h?rev=301939&r1=301938&r2=301939&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h?rev=301939&r1=301938&r2=301939&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h (original)<br>
+++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h Tue May 2 12:14:31 2017<br>
@@ -62,6 +62,7 @@ public:<br>
// since a user would write ":lo12:").<br>
VK_CALL = VK_ABS,<br>
VK_ABS_PAGE = VK_ABS | VK_PAGE,<br>
+ VK_ABS_PAGE_NC = VK_ABS | VK_PAGE | VK_NC,<br>
VK_ABS_G3 = VK_ABS | VK_G3,<br>
VK_ABS_G2 = VK_ABS | VK_G2,<br>
VK_ABS_G2_S = VK_SABS | VK_G2,<br>
@@ -95,7 +96,7 @@ public:<br>
VK_TPREL_HI12 = VK_TPREL | VK_HI12,<br>
VK_TPREL_LO12 = VK_TPREL | VK_PAGEOFF,<br>
VK_TPREL_LO12_NC = VK_TPREL | VK_PAGEOFF | VK_NC,<br>
- VK_TLSDESC_LO12 = VK_TLSDESC | VK_PAGEOFF | VK_NC,<br>
+ VK_TLSDESC_LO12 = VK_TLSDESC | VK_PAGEOFF,<br>
VK_TLSDESC_PAGE = VK_TLSDESC | VK_PAGE,<br>
<br>
VK_INVALID = 0xfff<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-tls-dynamics.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-tls-dynamics.ll?rev=301939&r1=301938&r2=301939&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-tls-dynamics.ll?rev=301939&r1=301938&r2=301939&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/arm64-tls-dynamics.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/arm64-tls-dynamics.ll Tue May 2 12:14:31 2017<br>
@@ -30,13 +30,13 @@ define i32 @test_generaldynamic() {<br>
; CHECK-NOLD: ldr w0, [x[[TP]], x0]<br>
<br>
; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21<br>
-; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC<br>
-; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC<br>
+; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12<br>
+; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12<br>
; CHECK-RELOC: R_AARCH64_TLSDESC_CALL<br>
<br>
; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21<br>
-; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC<br>
-; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC<br>
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12<br>
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12<br>
; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL<br>
<br>
}<br>
@@ -56,13 +56,13 @@ define i32* @test_generaldynamic_addr()<br>
; CHECK: add x0, [[TP]], x0<br>
<br>
; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21<br>
-; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC<br>
-; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC<br>
+; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12<br>
+; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12<br>
; CHECK-RELOC: R_AARCH64_TLSDESC_CALL<br>
<br>
; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21<br>
-; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC<br>
-; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC<br>
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12<br>
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12<br>
; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL<br>
<br>
}<br>
@@ -95,15 +95,15 @@ define i32 @test_localdynamic() {<br>
<br>
<br>
; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21<br>
-; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC<br>
-; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC<br>
+; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12<br>
+; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12<br>
; CHECK-RELOC: R_AARCH64_TLSDESC_CALL<br>
; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_HI12<br>
; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC<br>
<br>
; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21<br>
-; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC<br>
-; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC<br>
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12<br>
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12<br>
; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL<br>
<br>
}<br>
@@ -131,15 +131,15 @@ define i32* @test_localdynamic_addr() {<br>
ret i32* @local_dynamic_var<br>
<br>
; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21<br>
-; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC<br>
-; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC<br>
+; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12<br>
+; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12<br>
; CHECK-RELOC: R_AARCH64_TLSDESC_CALL<br>
; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_HI12<br>
; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC<br>
<br>
; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21<br>
-; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC<br>
-; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC<br>
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12<br>
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12<br>
; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL<br>
}<br>
<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/adrp-relocation.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/adrp-relocation.s?rev=301939&r1=301938&r2=301939&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/adrp-relocation.s?rev=301939&r1=301938&r2=301939&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/AArch64/adrp-relocation.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/adrp-relocation.s Tue May 2 12:14:31 2017<br>
@@ -1,4 +1,6 @@<br>
// RUN: llvm-mc -triple=aarch64-linux-gnu -filetype=obj -o - %s| llvm-readobj -r - | FileCheck %s<br>
+// RUN: llvm-mc -target-abi=ilp32 -triple=aarch64-linux-gnu -filetype=obj \<br>
+// RUN: -o - %s| llvm-readobj -r - | FileCheck -check-prefix=CHECK-ILP32 %s<br>
.text<br>
// These should produce an ADRP/ADD pair to calculate the address of<br>
// testfn. The important point is that LLVM shouldn't think it can deal with the<br>
@@ -16,3 +18,7 @@ sym:<br>
// CHECK: R_AARCH64_ADR_GOT_PAGE sym<br>
// CHECK: R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 sym<br>
// CHECK: R_AARCH64_TLSDESC_ADR_PAGE21 sym<br>
+// CHECK-ILP32: R_AARCH64_P32_ADR_PREL_PG_HI21 sym<br>
+// CHECK-ILP32: R_AARCH64_P32_ADR_GOT_PAGE sym<br>
+// CHECK-ILP32: R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21 sym<br>
+// CHECK-ILP32: R_AARCH64_P32_TLSDESC_ADR_PAGE21 sym<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/arm32-elf-relocs.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm32-elf-relocs.s?rev=301939&r1=301938&r2=301939&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm32-elf-relocs.s?rev=301939&r1=301938&r2=301939&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/AArch64/arm32-elf-relocs.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/arm32-elf-relocs.s Tue May 2 12:14:31 2017<br>
@@ -1,4 +1,7 @@<br>
-// RUN: llvm-mc -triple=arm64-linux-gnu -o - < %s | FileCheck %s<br>
+// RUN: llvm-mc -target-abi=ilp32 -triple=arm64-linux-gnu -o - < %s | \<br>
+// RUN: FileCheck %s<br>
+// RUN: llvm-mc -target-abi=ilp32 -triple=arm64-linux-gnu -show-encoding \<br>
+// RUN: -o - < %s | FileCheck --check-prefix=CHECK-ENCODING %s<br>
// RUN: llvm-mc -target-abi=ilp32 -triple=arm64-linux-gnu -filetype=obj < %s | \<br>
// RUN: llvm-objdump -triple=arm64-linux-gnu - -r | \<br>
// RUN: FileCheck %s --check-prefix=CHECK-OBJ-ILP32<br>
@@ -25,7 +28,7 @@<br>
<br>
add x5, x0, #:tlsdesc_lo12:sym<br>
// CHECK: add x5, x0, :tlsdesc_lo12:sym<br>
-// CHECK-OBJ-ILP32: 14 R_AARCH64_P32_TLSDESC_ADD_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: 14 R_AARCH64_P32_TLSDESC_ADD_LO12 sym<br>
<br>
add x0, x2, #:lo12:sym+8<br>
// CHECK: add x0, x2, :lo12:sym<br>
@@ -49,33 +52,33 @@<br>
<br>
add x5, x0, #:tlsdesc_lo12:sym+70<br>
// CHECK: add x5, x0, :tlsdesc_lo12:sym+70<br>
-// CHECK-OBJ-ILP32: 2c R_AARCH64_P32_TLSDESC_ADD_LO12_NC sym+70<br>
+// CHECK-OBJ-ILP32: 2c R_AARCH64_P32_TLSDESC_ADD_LO12 sym+70<br>
<br>
.hword sym + 4 - .<br>
// CHECK-OBJ-ILP32: 30 R_AARCH64_P32_PREL16 sym+4<br>
.word sym - . + 8<br>
-// CHECK-OBJ-ILP32 32 R_AARCH64_P32_PREL32 sym+8<br>
+// CHECK-OBJ-ILP32: 32 R_AARCH64_P32_PREL32 sym+8<br>
<br>
.hword sym<br>
-// CHECK-OBJ-ILP32 3e R_AARCH64_P32_ABS16 sym<br>
+// CHECK-OBJ-ILP32: 36 R_AARCH64_P32_ABS16 sym<br>
.word sym+1<br>
-// CHECK-OBJ-ILP32 40 R_AARCH64_P32_ABS32 sym+1<br>
+// CHECK-OBJ-ILP32: 38 R_AARCH64_P32_ABS32 sym+1<br>
<br>
adrp x0, sym<br>
// CHECK: adrp x0, sym<br>
-// CHECK-OBJ-ILP32 4c R_AARCH64_P32_ADR_PREL_PG_HI21 sym<br>
+// CHECK-OBJ-ILP32: 3c R_AARCH64_P32_ADR_PREL_PG_HI21 sym<br>
<br>
adrp x15, :got:sym<br>
// CHECK: adrp x15, :got:sym<br>
-// CHECK-OBJ-ILP32 50 R_AARCH64_P32_ADR_GOT_PAGE sym<br>
+// CHECK-OBJ-ILP32: 40 R_AARCH64_P32_ADR_GOT_PAGE sym<br>
<br>
adrp x29, :gottprel:sym<br>
// CHECK: adrp x29, :gottprel:sym<br>
-// CHECK-OBJ-ILP32 54 R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21 sym<br>
+// CHECK-OBJ-ILP32: 44 R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21 sym<br>
<br>
adrp x2, :tlsdesc:sym<br>
// CHECK: adrp x2, :tlsdesc:sym<br>
-// CHECK-OBJ-ILP32 58 R_AARCH64_P32_TLSDESC_ADR_PAGE21 sym<br>
+// CHECK-OBJ-ILP32: 48 R_AARCH64_P32_TLSDESC_ADR_PAGE21 sym<br>
<br>
// LLVM is not competent enough to do this relocation because the<br>
// page boundary could occur anywhere after linking. A relocation<br>
@@ -84,7 +87,7 @@<br>
.global trickQuestion<br>
trickQuestion:<br>
// CHECK: adrp x3, trickQuestion<br>
-// CHECK-OBJ-ILP32 5c R_AARCH64_P32_ADR_PREL_PG_HI21 trickQuestion<br>
+// CHECK-OBJ-ILP32: 4c R_AARCH64_P32_ADR_PREL_PG_HI21 trickQuestion<br>
<br>
ldrb w2, [x3, :lo12:sym]<br>
ldrsb w5, [x7, #:lo12:sym]<br>
@@ -94,10 +97,10 @@ trickQuestion:<br>
// CHECK: ldrsb w5, [x7, :lo12:sym]<br>
// CHECK: ldrsb x11, [x13, :lo12:sym]<br>
// CHECK: ldr b17, [x19, :lo12:sym]<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST8_ABS_LO12_NC sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST8_ABS_LO12_NC sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST8_ABS_LO12_NC sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST8_ABS_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST8_ABS_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST8_ABS_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST8_ABS_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST8_ABS_LO12_NC sym<br>
<br>
ldrb w23, [x29, #:dtprel_lo12_nc:sym]<br>
ldrsb w23, [x19, #:dtprel_lo12:sym]<br>
@@ -107,10 +110,10 @@ trickQuestion:<br>
// CHECK: ldrsb w23, [x19, :dtprel_lo12:sym]<br>
// CHECK: ldrsb x17, [x13, :dtprel_lo12_nc:sym]<br>
// CHECK: ldr b11, [x7, :dtprel_lo12:sym]<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 sym<br>
<br>
ldrb w1, [x2, :tprel_lo12:sym]<br>
ldrsb w3, [x4, #:tprel_lo12_nc:sym]<br>
@@ -120,10 +123,10 @@ trickQuestion:<br>
// CHECK: ldrsb w3, [x4, :tprel_lo12_nc:sym]<br>
// CHECK: ldrsb x5, [x6, :tprel_lo12:sym]<br>
// CHECK: ldr b7, [x8, :tprel_lo12_nc:sym]<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC sym<br>
<br>
ldrh w2, [x3, #:lo12:sym]<br>
ldrsh w5, [x7, :lo12:sym]<br>
@@ -133,10 +136,10 @@ trickQuestion:<br>
// CHECK: ldrsh w5, [x7, :lo12:sym]<br>
// CHECK: ldrsh x11, [x13, :lo12:sym]<br>
// CHECK: ldr h17, [x19, :lo12:sym]<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST16_ABS_LO12_NC sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST16_ABS_LO12_NC sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST16_ABS_LO12_NC sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST16_ABS_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST16_ABS_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST16_ABS_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST16_ABS_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST16_ABS_LO12_NC sym<br>
<br>
ldrh w23, [x29, #:dtprel_lo12_nc:sym]<br>
ldrsh w23, [x19, :dtprel_lo12:sym]<br>
@@ -146,10 +149,10 @@ trickQuestion:<br>
// CHECK: ldrsh w23, [x19, :dtprel_lo12:sym]<br>
// CHECK: ldrsh x17, [x13, :dtprel_lo12_nc:sym]<br>
// CHECK: ldr h11, [x7, :dtprel_lo12:sym]<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 sym<br>
<br>
ldrh w1, [x2, :tprel_lo12:sym]<br>
ldrsh w3, [x4, #:tprel_lo12_nc:sym]<br>
@@ -159,10 +162,10 @@ trickQuestion:<br>
// CHECK: ldrsh w3, [x4, :tprel_lo12_nc:sym]<br>
// CHECK: ldrsh x5, [x6, :tprel_lo12:sym]<br>
// CHECK: ldr h7, [x8, :tprel_lo12_nc:sym]<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC sym<br>
<br>
ldr w1, [x2, #:lo12:sym]<br>
ldrsw x3, [x4, #:lo12:sym]<br>
@@ -170,9 +173,9 @@ trickQuestion:<br>
// CHECK: ldr w1, [x2, :lo12:sym]<br>
// CHECK: ldrsw x3, [x4, :lo12:sym]<br>
// CHECK: ldr s4, [x5, :lo12:sym]<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST32_ABS_LO12_NC sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST32_ABS_LO12_NC sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST32_ABS_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST32_ABS_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST32_ABS_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST32_ABS_LO12_NC sym<br>
<br>
ldr w1, [x2, :dtprel_lo12:sym]<br>
ldrsw x3, [x4, #:dtprel_lo12_nc:sym]<br>
@@ -180,9 +183,9 @@ trickQuestion:<br>
// CHECK: ldr w1, [x2, :dtprel_lo12:sym]<br>
// CHECK: ldrsw x3, [x4, :dtprel_lo12_nc:sym]<br>
// CHECK: ldr s4, [x5, :dtprel_lo12_nc:sym]<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12 sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12 sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC sym<br>
<br>
<br>
ldr w1, [x2, #:tprel_lo12:sym]<br>
@@ -191,53 +194,69 @@ trickQuestion:<br>
// CHECK: ldr w1, [x2, :tprel_lo12:sym]<br>
// CHECK: ldrsw x3, [x4, :tprel_lo12_nc:sym]<br>
// CHECK: ldr s4, [x5, :tprel_lo12_nc:sym]<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12 sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12 sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC sym<br>
<br>
ldr x28, [x27, :lo12:sym]<br>
- ldr d26, [x25, #:lo12:sym]<br>
+ ldr d26, [x25, :lo12:sym]<br>
// CHECK: ldr x28, [x27, :lo12:sym]<br>
// CHECK: ldr d26, [x25, :lo12:sym]<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST64_ABS_LO12_NC sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST64_ABS_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST64_ABS_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST64_ABS_LO12_NC sym<br>
<br>
- ldr x24, [x23, #:got_lo12:sym]<br>
- ldr d22, [x21, :got_lo12:sym]<br>
-// CHECK: ldr x24, [x23, :got_lo12:sym]<br>
-// CHECK: ldr d22, [x21, :got_lo12:sym]<br>
-// CHECK-OBJ-ILP32 R_AARCH64_LD32_GOT_LO12_NC sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_LD32_GOT_LO12_NC sym<br>
+ ldr w24, [x23, :got_lo12:sym]<br>
+ ldr s22, [x21, :got_lo12:sym]<br>
+// CHECK: ldr w24, [x23, :got_lo12:sym]<br>
+// CHECK: ldr s22, [x21, :got_lo12:sym]<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_LD32_GOT_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_LD32_GOT_LO12_NC sym<br>
<br>
ldr x24, [x23, :dtprel_lo12_nc:sym]<br>
- ldr d22, [x21, #:dtprel_lo12:sym]<br>
+ ldr d22, [x21, :dtprel_lo12:sym]<br>
// CHECK: ldr x24, [x23, :dtprel_lo12_nc:sym]<br>
// CHECK: ldr d22, [x21, :dtprel_lo12:sym]<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12_NC sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12 sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12 sym<br>
<br>
- ldr x24, [x23, #:tprel_lo12:sym]<br>
+ ldr q24, [x23, :dtprel_lo12_nc:sym]<br>
+ ldr q22, [x21, :dtprel_lo12:sym]<br>
+// CHECK: ldr q24, [x23, :dtprel_lo12_nc:sym]<br>
+// CHECK: ldr q22, [x21, :dtprel_lo12:sym]<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12 sym<br>
+<br>
+ ldr x24, [x23, :tprel_lo12:sym]<br>
ldr d22, [x21, :tprel_lo12_nc:sym]<br>
// CHECK: ldr x24, [x23, :tprel_lo12:sym]<br>
// CHECK: ldr d22, [x21, :tprel_lo12_nc:sym]<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12 sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC sym<br>
-<br>
-# ldr x24, [x23, :gottprel_lo12:sym]<br>
-# ldr d22, [x21, #:gottprel_lo12:sym]<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12 sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC sym<br>
<br>
- ldr x24, [x23, #:tlsdesc_lo12:sym]<br>
- ldr d22, [x21, :tlsdesc_lo12:sym]<br>
-// CHECK: ldr x24, [x23, :tlsdesc_lo12:sym]<br>
-// CHECK: ldr d22, [x21, :tlsdesc_lo12:sym]<br>
-// Why is there a "_NC" at the end? "ELF for the ARM 64-bit architecture<br>
-// (AArch64) beta" doesn't have that.<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSDESC_LD32_LO12_NC sym<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSDESC_LD64_LO12_NC sym<br>
+ ldr q24, [x23, :tprel_lo12:sym]<br>
+ ldr q22, [x21, :tprel_lo12_nc:sym]<br>
+// CHECK: ldr q24, [x23, :tprel_lo12:sym]<br>
+// CHECK: ldr q22, [x21, :tprel_lo12_nc:sym]<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12 sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12_NC sym<br>
+<br>
+ ldr w24, [x23, :gottprel_lo12:sym]<br>
+ ldr s22, [x21, :gottprel_lo12:sym]<br>
+<br>
+ ldr w24, [x23, :tlsdesc_lo12:sym]<br>
+ ldr s22, [x21, :tlsdesc_lo12:sym]<br>
+// CHECK: ldr w24, [x23, :tlsdesc_lo12:sym]<br>
+// CHECK: ldr s22, [x21, :tlsdesc_lo12:sym]<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSDESC_LD32_LO12 sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSDESC_LD32_LO12 sym<br>
<br>
ldr q20, [x19, #:lo12:sym]<br>
// CHECK: ldr q20, [x19, :lo12:sym]<br>
-// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST128_ABS_LO12_NC sym<br>
+// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST128_ABS_LO12_NC sym<br>
+// check encoding here, since encoding test doesn't belong with TLS encoding<br>
+// tests, as it isn't a TLS relocation.<br>
+// CHECK-ENCODING: ldr q20, [x19, :lo12:sym] // encoding: [0x74,0bAAAAAA10,0b11AAAAAA,0x3d]<br>
+// CHECK-ENCODING-NEXT: 0, value: :lo12:sym, kind: fixup_aarch64_ldst_imm12_scale16<br>
<br>
// Since relocated instructions print without a '#', that syntax should<br>
// certainly be accepted when assembling.<br>
<br>
Added: llvm/trunk/test/MC/AArch64/arm32-large-relocs.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm32-large-relocs.s?rev=301939&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm32-large-relocs.s?rev=301939&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/AArch64/arm32-large-relocs.s (added)<br>
+++ llvm/trunk/test/MC/AArch64/arm32-large-relocs.s Tue May 2 12:14:31 2017<br>
@@ -0,0 +1,31 @@<br>
+// RUN: llvm-mc -target-abi=ilp32 -triple=arm64-linux-gnu -show-encoding -o - \<br>
+// RUN: %s \<br>
+// RUN: | FileCheck %s<br>
+// RUN: llvm-mc -target-abi=ilp32 -triple=arm64-linux-gnu -show-encoding \<br>
+// RUN: -filetype=obj -o - %s \<br>
+// RUN: | llvm-objdump -r - \<br>
+// RUN: | FileCheck --check-prefix=CHECK-OBJ %s<br>
+<br>
+ movz x2, #:abs_g0:sym<br>
+ movk w3, #:abs_g0_nc:sym<br>
+ movz x13, #:abs_g0_s:sym<br>
+ movn x17, #:abs_g0_s:sym<br>
+// CHECK: movz x2, #:abs_g0:sym // encoding: [0bAAA00010,A,0b100AAAAA,0xd2]<br>
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0:sym, kind: fixup_aarch64_movw<br>
+// CHECK: movk w3, #:abs_g0_nc:sym // encoding: [0bAAA00011,A,0b100AAAAA,0x72]<br>
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_nc:sym, kind: fixup_aarch64_movw<br>
+// CHECK: movz x13, #:abs_g0_s:sym // encoding: [0bAAA01101,A,0b100AAAAA,0xd2]<br>
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_aarch64_movw<br>
+// CHECK: movn x17, #:abs_g0_s:sym // encoding: [0bAAA10001,A,0b100AAAAA,0x92]<br>
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_aarch64_movw<br>
+<br>
+// CHECK-OBJ: 0 R_AARCH64_P32_MOVW_UABS_G0 sym<br>
+// CHECK-OBJ: 4 R_AARCH64_P32_MOVW_UABS_G0_NC sym<br>
+// CHECK-OBJ: 8 R_AARCH64_P32_MOVW_SABS_G0 sym<br>
+// CHECK-OBJ: c R_AARCH64_P32_MOVW_SABS_G0 sym<br>
+<br>
+ movz x4, #:abs_g1:sym<br>
+// CHECK: movz x4, #:abs_g1:sym // encoding: [0bAAA00100,A,0b101AAAAA,0xd2]<br>
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1:sym, kind: fixup_aarch64_movw<br>
+<br>
+// CHECK-OBJ: 10 R_AARCH64_P32_MOVW_UABS_G1 sym<br>
<br>
Added: llvm/trunk/test/MC/AArch64/arm32-tls-relocs.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm32-tls-relocs.s?rev=301939&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm32-tls-relocs.s?rev=301939&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/AArch64/arm32-tls-relocs.s (added)<br>
+++ llvm/trunk/test/MC/AArch64/arm32-tls-relocs.s Tue May 2 12:14:31 2017<br>
@@ -0,0 +1,290 @@<br>
+// RUN: llvm-mc -target-abi=ilp32 -triple=arm64-none-linux-gnu \<br>
+// RUN: -show-encoding < %s | FileCheck --check-prefix=CHECK-ILP32 %s<br>
+// RUN: llvm-mc -target-abi=ilp32 -triple=arm64-none-linux-gnu \<br>
+// RUN: -filetype=obj < %s -o - | \<br>
+// RUN: llvm-readobj -r -t | FileCheck --check-prefix=CHECK-ELF-ILP32 %s<br>
+<br>
+////////////////////////////////////////////////////////////////////////////////<br>
+// TLS initial-exec forms<br>
+////////////////////////////////////////////////////////////////////////////////<br>
+<br>
+ adrp x11, :gottprel:var<br>
+ ldr w10, [x0, #:gottprel_lo12:var]<br>
+ ldr w9, :gottprel:var<br>
+// CHECK-ILP32: adrp x11, :gottprel:var // encoding: [0x0b'A',A,A,0x90'A']<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_aarch64_pcrel_adrp_imm21<br>
+// CHECK-ILP32: ldr w10, [x0, :gottprel_lo12:var] // encoding: [0x0a,0bAAAAAA00,0b01AAAAAA,0xb9]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :gottprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale4<br>
+// CHECK-ILP32: ldr w9, :gottprel:var // encoding: [0bAAA01001,A,A,0x18]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_aarch64_ldr_pcrel_imm19<br>
+<br>
+// CHECK-ELF-ILP32: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21 [[VARSYM:[^ ]+]]<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC [[VARSYM]]<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSIE_LD_GOTTPREL_PREL19 [[VARSYM]]<br>
+<br>
+<br>
+////////////////////////////////////////////////////////////////////////////////<br>
+// TLS local-exec forms<br>
+////////////////////////////////////////////////////////////////////////////////<br>
+<br>
+ movz x5, #:tprel_g1:var<br>
+ movn x6, #:tprel_g1:var<br>
+ movz w7, #:tprel_g1:var<br>
+// CHECK-ILP32: movz x5, #:tprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw<br>
+// CHECK-ILP32: movn x6, #:tprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw<br>
+// CHECK-ILP32: movz w7, #:tprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw<br>
+<br>
+// CHECK-ELF-ILP32: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_MOVW_TPREL_G1 [[VARSYM]]<br>
+// CHECK-ELF-ILP32: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_MOVW_TPREL_G1 [[VARSYM]]<br>
+// CHECK-ELF-ILP32: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_MOVW_TPREL_G1 [[VARSYM]]<br>
+<br>
+<br>
+ movz x11, #:tprel_g0:var<br>
+ movn x12, #:tprel_g0:var<br>
+ movz w13, #:tprel_g0:var<br>
+// CHECK-ILP32: movz x11, #:tprel_g0:var // encoding: [0bAAA01011,A,0b100AAAAA,0x92]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw<br>
+// CHECK-ILP32: movn x12, #:tprel_g0:var // encoding: [0bAAA01100,A,0b100AAAAA,0x92]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw<br>
+// CHECK-ILP32: movz w13, #:tprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw<br>
+<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_MOVW_TPREL_G0 [[VARSYM]]<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_MOVW_TPREL_G0 [[VARSYM]]<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_MOVW_TPREL_G0 [[VARSYM]]<br>
+<br>
+<br>
+ movk w15, #:tprel_g0_nc:var<br>
+ movk w16, #:tprel_g0_nc:var<br>
+// CHECK-ILP32: movk w15, #:tprel_g0_nc:var // encoding: [0bAAA01111,A,0b100AAAAA,0x72]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_aarch64_movw<br>
+// CHECK-ILP32: movk w16, #:tprel_g0_nc:var // encoding: [0bAAA10000,A,0b100AAAAA,0x72]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_aarch64_movw<br>
+<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]]<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]]<br>
+<br>
+<br>
+ add x21, x22, #:tprel_lo12:var<br>
+// CHECK-ILP32: add x21, x22, :tprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_add_imm12<br>
+<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_ADD_TPREL_LO12 [[VARSYM]]<br>
+<br>
+<br>
+ add x25, x26, #:tprel_lo12_nc:var<br>
+// CHECK-ILP32: add x25, x26, :tprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_add_imm12<br>
+<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC [[VARSYM]]<br>
+<br>
+<br>
+ ldrb w29, [x30, #:tprel_lo12:var]<br>
+ ldrsb x29, [x28, #:tprel_lo12_nc:var]<br>
+// CHECK-ILP32: ldrb w29, [x30, :tprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale1<br>
+// CHECK-ILP32: ldrsb x29, [x28, :tprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale1<br>
+<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 [[VARSYM]]<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC [[VARSYM]]<br>
+<br>
+<br>
+ strh w27, [x26, #:tprel_lo12:var]<br>
+ ldrsh x25, [x24, #:tprel_lo12_nc:var]<br>
+// CHECK-ILP32: strh w27, [x26, :tprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale2<br>
+// CHECK-ILP32: ldrsh x25, [x24, :tprel_lo12_nc:var] // encoding: [0x19,0bAAAAAA11,0b10AAAAAA,0x79]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale2<br>
+<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 [[VARSYM]]<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC [[VARSYM]]<br>
+<br>
+<br>
+ ldr w23, [x22, #:tprel_lo12:var]<br>
+ ldrsw x21, [x20, #:tprel_lo12_nc:var]<br>
+// CHECK-ILP32: ldr w23, [x22, :tprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale4<br>
+// CHECK-ILP32: ldrsw x21, [x20, :tprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale4<br>
+<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12 [[VARSYM]]<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC [[VARSYM]]<br>
+<br>
+ ldr x19, [x18, #:tprel_lo12:var]<br>
+ str x17, [x16, #:tprel_lo12_nc:var]<br>
+// CHECK-ILP32: ldr x19, [x18, :tprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8<br>
+// CHECK-ILP32: str x17, [x16, :tprel_lo12_nc:var] // encoding: [0x11,0bAAAAAA10,0b00AAAAAA,0xf9]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale8<br>
+<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12 [[VARSYM]]<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC [[VARSYM]]<br>
+<br>
+<br>
+ ldr q24, [x23, :tprel_lo12:var]<br>
+ str q22, [x21, :tprel_lo12_nc:var]<br>
+// CHECK-ILP32: ldr q24, [x23, :tprel_lo12:var] // encoding: [0xf8,0bAAAAAA10,0b11AAAAAA,0x3d]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale16<br>
+// CHECK-ILP32: str q22, [x21, :tprel_lo12_nc:var] // encoding: [0xb6,0bAAAAAA10,0b10AAAAAA,0x3d]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale16<br>
+<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12 [[VARSYM]]<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12_NC [[VARSYM]]<br>
+<br>
+////////////////////////////////////////////////////////////////////////////////<br>
+// TLS local-dynamic forms<br>
+////////////////////////////////////////////////////////////////////////////////<br>
+<br>
+ movz x5, #:dtprel_g1:var<br>
+ movn x6, #:dtprel_g1:var<br>
+ movz w7, #:dtprel_g1:var<br>
+// CHECK-ILP32: movz x5, #:dtprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw<br>
+// CHECK-ILP32: movn x6, #:dtprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw<br>
+// CHECK-ILP32: movz w7, #:dtprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw<br>
+<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_MOVW_DTPREL_G1 [[VARSYM]]<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_MOVW_DTPREL_G1 [[VARSYM]]<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_MOVW_DTPREL_G1 [[VARSYM]]<br>
+<br>
+<br>
+ movz x11, #:dtprel_g0:var<br>
+ movn x12, #:dtprel_g0:var<br>
+ movz w13, #:dtprel_g0:var<br>
+// CHECK-ILP32: movz x11, #:dtprel_g0:var // encoding: [0bAAA01011,A,0b100AAAAA,0x92]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw<br>
+// CHECK-ILP32: movn x12, #:dtprel_g0:var // encoding: [0bAAA01100,A,0b100AAAAA,0x92]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw<br>
+// CHECK-ILP32: movz w13, #:dtprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw<br>
+<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0 [[VARSYM]]<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0 [[VARSYM]]<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0 [[VARSYM]]<br>
+<br>
+<br>
+ movk x15, #:dtprel_g0_nc:var<br>
+ movk w16, #:dtprel_g0_nc:var<br>
+// CHECK-ILP32: movk x15, #:dtprel_g0_nc:var // encoding: [0bAAA01111,A,0b100AAAAA,0xf2]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_aarch64_movw<br>
+// CHECK-ILP32: movk w16, #:dtprel_g0_nc:var // encoding: [0bAAA10000,A,0b100AAAAA,0x72]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_aarch64_movw<br>
+<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]]<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]]<br>
+<br>
+<br>
+ add x21, x22, #:dtprel_lo12:var<br>
+// CHECK-ILP32: add x21, x22, :dtprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_add_imm12<br>
+<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12 [[VARSYM]]<br>
+<br>
+<br>
+ add x25, x26, #:dtprel_lo12_nc:var<br>
+// CHECK-ILP32: add x25, x26, :dtprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_add_imm12<br>
+<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12_NC [[VARSYM]]<br>
+<br>
+<br>
+ add x0, x0, #:dtprel_hi12:var_tlsld, lsl #12<br>
+ add x0, x0, #:tprel_hi12:var_tlsle, lsl #12<br>
+<br>
+// CHECK-ELF-ILP32: R_AARCH64_P32_TLSLD_ADD_DTPREL_HI12 var_tlsld<br>
+// CHECK-ELF-ILP32: R_AARCH64_P32_TLSLE_ADD_TPREL_HI12 var_tlsle<br>
+<br>
+<br>
+ ldrb w29, [x30, #:dtprel_lo12:var]<br>
+ ldrsb x29, [x28, #:dtprel_lo12_nc:var]<br>
+// CHECK-ILP32: ldrb w29, [x30, :dtprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale1<br>
+// CHECK-ILP32: ldrsb x29, [x28, :dtprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale1<br>
+<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 [[VARSYM]]<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC [[VARSYM]]<br>
+<br>
+<br>
+ strh w27, [x26, #:dtprel_lo12:var]<br>
+ ldrsh x25, [x24, #:dtprel_lo12_nc:var]<br>
+// CHECK-ILP32: strh w27, [x26, :dtprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale2<br>
+// CHECK-ILP32: ldrsh x25, [x24, :dtprel_lo12_nc:var] // encoding: [0x19,0bAAAAAA11,0b10AAAAAA,0x79]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale2<br>
+<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 [[VARSYM]]<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC [[VARSYM]]<br>
+<br>
+<br>
+ ldr w23, [x22, #:dtprel_lo12:var]<br>
+ ldrsw x21, [x20, #:dtprel_lo12_nc:var]<br>
+// CHECK-ILP32: ldr w23, [x22, :dtprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale4<br>
+// CHECK-ILP32: ldrsw x21, [x20, :dtprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale4<br>
+<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12 [[VARSYM]]<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC [[VARSYM]]<br>
+<br>
+ ldr x19, [x18, #:dtprel_lo12:var]<br>
+ str x17, [x16, #:dtprel_lo12_nc:var]<br>
+// CHECK-ILP32: ldr x19, [x18, :dtprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8<br>
+// CHECK-ILP32: str x17, [x16, :dtprel_lo12_nc:var] // encoding: [0x11,0bAAAAAA10,0b00AAAAAA,0xf9]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale8<br>
+<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12 [[VARSYM]]<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12_NC [[VARSYM]]<br>
+<br>
+ ldr q24, [x23, #:dtprel_lo12:var]<br>
+ str q22, [x21, #:dtprel_lo12_nc:var]<br>
+// CHECK-ILP32: ldr q24, [x23, :dtprel_lo12:var] // encoding: [0xf8,0bAAAAAA10,0b11AAAAAA,0x3d]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale16<br>
+// CHECK-ILP32: str q22, [x21, :dtprel_lo12_nc:var] // encoding: [0xb6,0bAAAAAA10,0b10AAAAAA,0x3d]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale16<br>
+<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12 [[VARSYM]]<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12_NC [[VARSYM]]<br>
+<br>
+////////////////////////////////////////////////////////////////////////////////<br>
+// TLS descriptor forms<br>
+////////////////////////////////////////////////////////////////////////////////<br>
+<br>
+ adrp x8, :tlsdesc:var<br>
+ ldr w7, [x6, #:tlsdesc_lo12:var]<br>
+ add x5, x4, #:tlsdesc_lo12:var<br>
+ .tlsdesccall var<br>
+ blr x3<br>
+<br>
+// CHECK-ILP32: adrp x8, :tlsdesc:var // encoding: [0x08'A',A,A,0x90'A']<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_aarch64_pcrel_adrp_imm21<br>
+// CHECK-ILP32: ldr w7, [x6, :tlsdesc_lo12:var] // encoding: [0xc7,0bAAAAAA00,0b01AAAAAA,0xb9]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_aarch64_ldst_imm12_scale4<br>
+// CHECK-ILP32: add x5, x4, :tlsdesc_lo12:var // encoding: [0x85,0bAAAAAA00,0b00AAAAAA,0x91]<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_aarch64_add_imm12<br>
+// CHECK-ILP32: .tlsdesccall var // encoding: []<br>
+// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: var, kind: fixup_aarch64_tlsdesc_call<br>
+// CHECK-ILP32: blr x3 // encoding: [0x60,0x00,0x3f,0xd6]<br>
+<br>
+<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSDESC_ADR_PAGE21 [[VARSYM]]<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSDESC_LD32_LO12 [[VARSYM]]<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSDESC_ADD_LO12 [[VARSYM]]<br>
+// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSDESC_CALL [[VARSYM]]<br>
+<br>
+ // Make sure symbol 5 has type STT_TLS:<br>
+<br>
+// CHECK-ELF-ILP32: Symbols [<br>
+// CHECK-ELF-ILP32: Symbol {<br>
+// CHECK-ELF-ILP32: Name: var<br>
+// CHECK-ELF-ILP32-NEXT: Value:<br>
+// CHECK-ELF-ILP32-NEXT: Size:<br>
+// CHECK-ELF-ILP32-NEXT: Binding: Global<br>
+// CHECK-ELF-ILP32-NEXT: Type: TLS<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/arm64-elf-reloc-condbr.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-elf-reloc-condbr.s?rev=301939&r1=301938&r2=301939&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-elf-reloc-condbr.s?rev=301939&r1=301938&r2=301939&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/AArch64/arm64-elf-reloc-condbr.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/arm64-elf-reloc-condbr.s Tue May 2 12:14:31 2017<br>
@@ -1,5 +1,8 @@<br>
// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj %s -o - | \<br>
// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s<br>
+// RUN: llvm-mc -target-abi=ilp32 -triple=arm64-none-linux-gnu -filetype=obj \<br>
+// RUN: %s -o - | \<br>
+// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ-ILP32 %s<br>
<br>
b.eq somewhere<br>
<br>
@@ -8,3 +11,9 @@<br>
// OBJ-NEXT: 0x0 R_AARCH64_CONDBR19 somewhere 0x0<br>
// OBJ-NEXT: }<br>
// OBJ-NEXT: ]<br>
+<br>
+// OBJ-ILP32: Relocations [<br>
+// OBJ-ILP32-NEXT: Section {{.*}} .rela.text {<br>
+// OBJ-ILP32-NEXT: 0x0 R_AARCH64_P32_CONDBR19 somewhere 0x0<br>
+// OBJ-ILP32-NEXT: }<br>
+// OBJ-ILP32-NEXT: ]<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/arm64-elf-relocs.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-elf-relocs.s?rev=301939&r1=301938&r2=301939&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-elf-relocs.s?rev=301939&r1=301938&r2=301939&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/AArch64/arm64-elf-relocs.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/arm64-elf-relocs.s Tue May 2 12:14:31 2017<br>
@@ -1,5 +1,7 @@<br>
// RUN: llvm-mc -triple=arm64-linux-gnu -o - < %s | FileCheck %s<br>
-// RUN: llvm-mc -triple=arm64-linux-gnu -filetype=obj < %s | \<br>
+// RUN: llvm-mc -triple=arm64-linux-gnu -show-encoding -o - < %s | \<br>
+// RUN: FileCheck --check-prefix=CHECK-ENCODING %s<br>
+// RUN: llvm-mc -triple=arm64-linux-gnu -filetype=obj < %s | \<br>
// RUN: llvm-objdump -triple=arm64-linux-gnu - -r | \<br>
// RUN: FileCheck %s --check-prefix=CHECK-OBJ-LP64<br>
<br>
@@ -25,7 +27,7 @@<br>
<br>
add x5, x0, #:tlsdesc_lo12:sym<br>
// CHECK: add x5, x0, :tlsdesc_lo12:sym<br>
-// CHECK-OBJ-LP64: 14 R_AARCH64_TLSDESC_ADD_LO12_NC sym<br>
+// CHECK-OBJ-LP64: 14 R_AARCH64_TLSDESC_ADD_LO12 sym<br>
<br>
add x0, x2, #:lo12:sym+8<br>
// CHECK: add x0, x2, :lo12:sym<br>
@@ -49,37 +51,37 @@<br>
<br>
add x5, x0, #:tlsdesc_lo12:sym+70<br>
// CHECK: add x5, x0, :tlsdesc_lo12:sym+70<br>
-// CHECK-OBJ-LP64: 2c R_AARCH64_TLSDESC_ADD_LO12_NC sym+70<br>
+// CHECK-OBJ-LP64: 2c R_AARCH64_TLSDESC_ADD_LO12 sym+70<br>
<br>
.hword sym + 4 - .<br>
// CHECK-OBJ-LP64: 30 R_AARCH64_PREL16 sym+4<br>
.word sym - . + 8<br>
-// CHECK-OBJ-LP64 32 R_AARCH64_PREL32 sym+8<br>
+// CHECK-OBJ-LP64: 32 R_AARCH64_PREL32 sym+8<br>
.xword sym-.<br>
-// CHECK-OBJ-LP64 36 R_AARCH64_PREL64 sym{{$}}<br>
+// CHECK-OBJ-LP64: 36 R_AARCH64_PREL64 sym{{$}}<br>
<br>
.hword sym<br>
-// CHECK-OBJ-LP64 3e R_AARCH64_ABS16 sym<br>
+// CHECK-OBJ-LP64: 3e R_AARCH64_ABS16 sym<br>
.word sym+1<br>
-// CHECK-OBJ-LP64 40 R_AARCH64_ABS32 sym+1<br>
+// CHECK-OBJ-LP64: 40 R_AARCH64_ABS32 sym+1<br>
.xword sym+16<br>
-// CHECK-OBJ-LP64 44 R_AARCH64_ABS64 sym+16<br>
+// CHECK-OBJ-LP64: 44 R_AARCH64_ABS64 sym+16<br>
<br>
adrp x0, sym<br>
// CHECK: adrp x0, sym<br>
-// CHECK-OBJ-LP64 4c R_AARCH64_ADR_PREL_PG_HI21 sym<br>
+// CHECK-OBJ-LP64: 4c R_AARCH64_ADR_PREL_PG_HI21 sym<br>
<br>
adrp x15, :got:sym<br>
// CHECK: adrp x15, :got:sym<br>
-// CHECK-OBJ-LP64 50 R_AARCH64_ADR_GOT_PAGE sym<br>
+// CHECK-OBJ-LP64: 50 R_AARCH64_ADR_GOT_PAGE sym<br>
<br>
adrp x29, :gottprel:sym<br>
// CHECK: adrp x29, :gottprel:sym<br>
-// CHECK-OBJ-LP64 54 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 sym<br>
+// CHECK-OBJ-LP64: 54 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 sym<br>
<br>
adrp x2, :tlsdesc:sym<br>
// CHECK: adrp x2, :tlsdesc:sym<br>
-// CHECK-OBJ-LP64 58 R_AARCH64_TLSDESC_ADR_PAGE21 sym<br>
+// CHECK-OBJ-LP64: 58 R_AARCH64_TLSDESC_ADR_PAGE21 sym<br>
<br>
// LLVM is not competent enough to do this relocation because the<br>
// page boundary could occur anywhere after linking. A relocation<br>
@@ -88,7 +90,7 @@<br>
.global trickQuestion<br>
trickQuestion:<br>
// CHECK: adrp x3, trickQuestion<br>
-// CHECK-OBJ-LP64 5c R_AARCH64_ADR_PREL_PG_HI21 trickQuestion<br>
+// CHECK-OBJ-LP64: 5c R_AARCH64_ADR_PREL_PG_HI21 trickQuestion<br>
<br>
ldrb w2, [x3, :lo12:sym]<br>
ldrsb w5, [x7, #:lo12:sym]<br>
@@ -98,10 +100,10 @@ trickQuestion:<br>
// CHECK: ldrsb w5, [x7, :lo12:sym]<br>
// CHECK: ldrsb x11, [x13, :lo12:sym]<br>
// CHECK: ldr b17, [x19, :lo12:sym]<br>
-// CHECK-OBJ-LP64 R_AARCH64_LDST8_ABS_LO12_NC sym<br>
-// CHECK-OBJ-LP64 R_AARCH64_LDST8_ABS_LO12_NC sym<br>
-// CHECK-OBJ-LP64 R_AARCH64_LDST8_ABS_LO12_NC sym<br>
-// CHECK-OBJ-LP64 R_AARCH64_LDST8_ABS_LO12_NC sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_LDST8_ABS_LO12_NC sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_LDST8_ABS_LO12_NC sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_LDST8_ABS_LO12_NC sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_LDST8_ABS_LO12_NC sym<br>
<br>
ldrb w23, [x29, #:dtprel_lo12_nc:sym]<br>
ldrsb w23, [x19, #:dtprel_lo12:sym]<br>
@@ -111,10 +113,10 @@ trickQuestion:<br>
// CHECK: ldrsb w23, [x19, :dtprel_lo12:sym]<br>
// CHECK: ldrsb x17, [x13, :dtprel_lo12_nc:sym]<br>
// CHECK: ldr b11, [x7, :dtprel_lo12:sym]<br>
-// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym<br>
-// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym<br>
-// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym<br>
-// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym<br>
<br>
ldrb w1, [x2, :tprel_lo12:sym]<br>
ldrsb w3, [x4, #:tprel_lo12_nc:sym]<br>
@@ -124,10 +126,10 @@ trickQuestion:<br>
// CHECK: ldrsb w3, [x4, :tprel_lo12_nc:sym]<br>
// CHECK: ldrsb x5, [x6, :tprel_lo12:sym]<br>
// CHECK: ldr b7, [x8, :tprel_lo12_nc:sym]<br>
-// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym<br>
-// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym<br>
-// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym<br>
-// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym<br>
<br>
ldrh w2, [x3, #:lo12:sym]<br>
ldrsh w5, [x7, :lo12:sym]<br>
@@ -137,10 +139,10 @@ trickQuestion:<br>
// CHECK: ldrsh w5, [x7, :lo12:sym]<br>
// CHECK: ldrsh x11, [x13, :lo12:sym]<br>
// CHECK: ldr h17, [x19, :lo12:sym]<br>
-// CHECK-OBJ-LP64 R_AARCH64_LDST16_ABS_LO12_NC sym<br>
-// CHECK-OBJ-LP64 R_AARCH64_LDST16_ABS_LO12_NC sym<br>
-// CHECK-OBJ-LP64 R_AARCH64_LDST16_ABS_LO12_NC sym<br>
-// CHECK-OBJ-LP64 R_AARCH64_LDST16_ABS_LO12_NC sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_LDST16_ABS_LO12_NC sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_LDST16_ABS_LO12_NC sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_LDST16_ABS_LO12_NC sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_LDST16_ABS_LO12_NC sym<br>
<br>
ldrh w23, [x29, #:dtprel_lo12_nc:sym]<br>
ldrsh w23, [x19, :dtprel_lo12:sym]<br>
@@ -150,10 +152,10 @@ trickQuestion:<br>
// CHECK: ldrsh w23, [x19, :dtprel_lo12:sym]<br>
// CHECK: ldrsh x17, [x13, :dtprel_lo12_nc:sym]<br>
// CHECK: ldr h11, [x7, :dtprel_lo12:sym]<br>
-// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym<br>
-// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym<br>
-// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym<br>
-// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym<br>
<br>
ldrh w1, [x2, :tprel_lo12:sym]<br>
ldrsh w3, [x4, #:tprel_lo12_nc:sym]<br>
@@ -163,10 +165,10 @@ trickQuestion:<br>
// CHECK: ldrsh w3, [x4, :tprel_lo12_nc:sym]<br>
// CHECK: ldrsh x5, [x6, :tprel_lo12:sym]<br>
// CHECK: ldr h7, [x8, :tprel_lo12_nc:sym]<br>
-// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym<br>
-// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym<br>
-// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym<br>
-// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym<br>
<br>
ldr w1, [x2, #:lo12:sym]<br>
ldrsw x3, [x4, #:lo12:sym]<br>
@@ -174,9 +176,9 @@ trickQuestion:<br>
// CHECK: ldr w1, [x2, :lo12:sym]<br>
// CHECK: ldrsw x3, [x4, :lo12:sym]<br>
// CHECK: ldr s4, [x5, :lo12:sym]<br>
-// CHECK-OBJ-LP64 R_AARCH64_LDST32_ABS_LO12_NC sym<br>
-// CHECK-OBJ-LP64 R_AARCH64_LDST32_ABS_LO12_NC sym<br>
-// CHECK-OBJ-LP64 R_AARCH64_LDST32_ABS_LO12_NC sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_LDST32_ABS_LO12_NC sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_LDST32_ABS_LO12_NC sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_LDST32_ABS_LO12_NC sym<br>
<br>
ldr w1, [x2, :dtprel_lo12:sym]<br>
ldrsw x3, [x4, #:dtprel_lo12_nc:sym]<br>
@@ -184,9 +186,9 @@ trickQuestion:<br>
// CHECK: ldr w1, [x2, :dtprel_lo12:sym]<br>
// CHECK: ldrsw x3, [x4, :dtprel_lo12_nc:sym]<br>
// CHECK: ldr s4, [x5, :dtprel_lo12_nc:sym]<br>
-// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST32_DTPREL_LO12 sym<br>
-// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym<br>
-// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST32_DTPREL_LO12 sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym<br>
+// CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym<br>
<br>
<br>
ldr w1, [x2, #:tprel_lo12:sym]<br>
@@ -195,55 +197,73 @@ trickQuestion:<br>
// CHECK: ldr w1, [x2, :tprel_lo12:sym]<br>
// CHECK: ldrsw x3, [x4, :tprel_lo12_nc:sym]<br>
// CHECK: ldr s4, [x5, :tprel_lo12_nc:sym]<br></blockquote></div>