[PATCH] D31944: [DAGCombiner] add (sext i1 X), 1 --> zext (not i1 X)

[Eli Friedman via Phabricator via llvm-commits]

efriedma accepted this revision.
efriedma added a comment.
This revision is now accepted and ready to land.

I think you've covered the interesting cases; LGTM.

> I was expecting ARM to match to 'vbic'

For sext_inc_vec?  It's doing the xor in the wrong width for it to match.  Try changing the return type of sext_inc_vec to `<4 x i64>`, and you'll see essentially the same thing on AVX2.


https://reviews.llvm.org/D31944