[PATCH] D31944: [DAGCombiner] add (sext i1 X), 1 --> zext (not i1 X)

[Sanjay Patel via Phabricator via llvm-commits]

spatel updated this revision to Diff 96742.
spatel added a comment.

Patch updated:
No code changes again, but added tests with:
https://reviews.llvm.org/rL301362 / https://reviews.llvm.org/rL301412
And improved 'true' detection with:
https://reviews.llvm.org/rL301408

I think all tests are improvements or neutral now. Let me know if I missed the intent on the new tests or if there's any other interesting pattern to look at. I was expecting ARM to match to 'vbic', but I'm not sure if that's better in practice than what we see here?


https://reviews.llvm.org/D31944

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/ARM/bool-ext-inc.ll
  test/CodeGen/X86/bool-ext-inc.ll

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