[PATCH] D30549: [X86][SSE] Lower 128-bit vectors to SIGN/ZERO_EXTEND_VECTOR_IN_REG ops.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: include/llvm/Target/TargetSelectionDAG.td:165
+  SDTCisInt<0>, SDTCisVec<0>, SDTCisInt<1>, SDTCisVec<1>,
+  SDTCisSameSizeAs<0,1>
+]>;
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Should this have SDTCisOpSmallerThanOp<1, 0> too?


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Comment at: lib/CodeGen/SelectionDAG/SelectionDAG.cpp:2449
   }
   case ISD::SIGN_EXTEND: {
     EVT InVT = Op.getOperand(0).getValueType();
----------------
Why no handling for ISD::SIGN_EXTEND_VECTOR_INREG?


Repository:
  rL LLVM

https://reviews.llvm.org/D30549