[PATCH] D29397: [DAGCombiner] Support bswap as a part of load combine patterns

Renato Golin via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Feb 1 09:18:13 PST 2017

rengolin added inline comments.

Comment at: test/CodeGen/ARM/load-combine-big-endian.ll:428
+; CHECK: ldr r0, [r0]
+; CHECK-NEXT: mov r1, #65280
+; CHECK-NEXT: mov r2, #16711680
filcab wrote:
> rengolin wrote:
> > I'm surprised this doesn't use `REV16`.
> `REV16` has `               Requires<[IsARM, HasV6]>,`, but from the run lines, it seems that the default for "arm" is probably before v6 (I tried looking for the default, but couldn't find it).
> Could that be it?
Ah, good catch! REV16 is available on ARMv6+, Thumb1, 2 and ARM (and our table gen descriptions have that already), but the check lines below are only for "arm" which is "ARMv4". 

This test is ok (has the CHECK-ARMv6) but the LE below has "CHECK64" which is why I got confused. :)

Comment at: test/CodeGen/ARM/load-combine.ll:395
+; CHECK64-LABEL: load_i32_by_bswap_i16:
+; CHECK64: ldr r0, [r0]
So we just need to fix the typo here: `CHECK64` -> `CHECK-ARMv6`


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