[PATCH] D28254: [AArch64][CostModel] Improve cost for fsqrt intrinsics.

[Chad Rosier via Phabricator via llvm-commits]

mcrosier added a comment.

Thanks for the feedback, Simon.  I'll experiment with using costs that are more representative of throughput as you suggest.



================
Comment at: lib/Target/AArch64/AArch64TargetTransformInfo.cpp:504
+    { ISD::FSQRT, MVT::v2f64, 5 },
+  };
+
----------------
RKSimon wrote:
> I don't know the range of costs that AARCH64 cores can have here - for x86 we tend to qualify these by mentioning the core type that we used for the costs in a comment. But AARCH64 is younger so might still be more consistent!
I think this makes sense, but the AArch64 backend has only a single generation of SIMD instructions (excluding the v8.[1|2]a extensions and the recently announced scalable vector extensions (VSE)).

We might consider predicating the logic based on the specific sub-target (e.g., Kryo, Cortex-A57) as opposed to the SIMD generation (e.g., SSE, MMX, AVX2) for AArch64.. at least in those cases where the latencies vary greatly between subtargets.


https://reviews.llvm.org/D28254