[PATCH] D27774: [ARM] Implement isExtractSubvectorCheap

[Renato Golin via Phabricator via llvm-commits]

rengolin accepted this revision.
rengolin added a comment.
This revision is now accepted and ready to land.

Hi Eli,

Just making sure the `vorr` can't move past the `vld1`s, LGTM. Thanks!

Looking forward to the follow up to fix `vpadd`.



================
Comment at: test/CodeGen/ARM/vext.ll:144
+;CHECK-NEXT: vld1.64
+;CHECK-NEXT: vld1.64
+;CHECK-NEXT: vorr
----------------
Currently, the `vmov.u16` gets moved in between the `vld1`s, so I worry that the compiler might try to do that again with the `vorr` and the `CHECK-NEXT` could fail.


Repository:
  rL LLVM

https://reviews.llvm.org/D27774