[PATCH] D27774: [ARM] Implement isExtractSubvectorCheap

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: test/CodeGen/ARM/vext.ll:144
+;CHECK-NEXT: vld1.64
+;CHECK-NEXT: vld1.64
+;CHECK-NEXT: vorr
----------------
rengolin wrote:
> Currently, the `vmov.u16` gets moved in between the `vld1`s, so I worry that the compiler might try to do that again with the `vorr` and the `CHECK-NEXT` could fail.
I think I'll just generate the checks using update_llc_test_checks.py to make it easy to regenerate if a scheduler change makes it move for some reason.  (I think we really need exhaustive checks for shuffles; it can be hard to spot regressions otherwise.)


Repository:
  rL LLVM

https://reviews.llvm.org/D27774