[PATCH] D23446: [X86] Enable setcc to srl(ctlz) transformation on btver2 architectures.

[Sanjay Patel via llvm-commits]

spatel accepted this revision.
spatel added a comment.
This revision is now accepted and ready to land.

LGTM. See inline for nits.



================
Comment at: lib/Target/X86/X86ISelLowering.cpp:4191
+bool X86TargetLowering::isCtlzFast() const {
+  return Subtarget.hasLZCNT() && Subtarget.hasFastLZCNT();
+}
----------------
Could remove or assert hasLZCNT()?


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:29105-29107
+  if (Ret) {
+    Ret = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0), Ret);
+  }
----------------
No need for braces here.


================
Comment at: test/CodeGen/X86/lzcnt-zext-cmp.ll:201
+
+; Test three 32-bit inputs, output is 32-bit, but compared to bar6 test,
+; %.cmp2 inputs' order is inverted.
----------------
Update name: "bar6"


https://reviews.llvm.org/D23446