[PATCH] D23446: [X86] Enable setcc to srl(ctlz) transformation on btver2 architectures.

[pierre gousseau via llvm-commits]

pgousseau added inline comments.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:4191
+bool X86TargetLowering::isCtlzFast() const {
+  return Subtarget.hasLZCNT() && Subtarget.hasFastLZCNT();
+}
----------------
spatel wrote:
> Could remove or assert hasLZCNT()?
Yes makes sense, will remove before commit.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:29105-29107
+  if (Ret) {
+    Ret = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0), Ret);
+  }
----------------
spatel wrote:
> No need for braces here.
Will remove before commit.


================
Comment at: test/CodeGen/X86/lzcnt-zext-cmp.ll:201
+
+; Test three 32-bit inputs, output is 32-bit, but compared to bar6 test,
+; %.cmp2 inputs' order is inverted.
----------------
spatel wrote:
> Update name: "bar6"
Thanks for spotting this, will fix before commit.


https://reviews.llvm.org/D23446