[PATCH] D21571: [AArch64] Avoid generating indexed vector instructions for Exynos

[Sebastian Pop via llvm-commits]

sebpop added inline comments.

================
Comment at: llvm/lib/Target/AArch64/AArch64VectorByElementOpt.cpp:171
@@ +170,3 @@
+  if (!shouldReplaceInstruction(MF, IndexMulMCID, DupMCID, MulMCID,
+                                VecInstElemTable))
+    return true;
----------------
This only checks for 1 pair of the current 12 pairs of instructions that may be replaced.
I think we should put all the 12 pairs in a vector and iterate through all of them.

================
Comment at: llvm/lib/Target/AArch64/AArch64VectorByElementOpt.cpp:224
@@ +223,3 @@
+    DupMCID = &TII->get(AArch64::DUPv4i32lane);
+    MulMCID = &TII->get(AArch64::FMLAv4f32);
+    break;
----------------
In that case the 12 cases currently handled can be refactored like this:
  (DupMCID, MulMCID) = find(MI.getOpcode())
Adding new transform patterns would be by adding them to the vector.


https://reviews.llvm.org/D21571