[PATCH] D21571: [AArch64] Avoid generating indexed vector instructions for Exynos

[Sebastian Pop via llvm-commits]

sebpop added inline comments.

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Comment at: llvm/lib/Target/AArch64/AArch64VectorByElementOpt.cpp:127
@@ +126,3 @@
+  if (!SchedModel.hasInstrSchedModel())
+    return false;
+
----------------
Please move the above 10 lines of code out of the loops to...

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Comment at: llvm/lib/Target/AArch64/AArch64VectorByElementOpt.cpp:341
@@ +340,3 @@
+  MRI = &MF.getRegInfo();
+
+  // A simple check to exit this pass early for targets that do not need it.
----------------
... move the code here.

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Comment at: llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll:2
@@ -1,1 +1,3 @@
 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast -mcpu=exynos-m1 | FileCheck --check-prefix=EXYNOS %s
+; The instruction latencies of Exynos-M1 triggers the transform we see under the Exynos check.
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flyingforyou wrote:
> I think more proper check-prefix is `EXYNOSM1`, if future exynos core has a possibility that can be different from now.
As EXYNOS is only a marker for FileCheck, I think it is not important to change to EXYNOSM1: it is clear from the -mcpu flag that these checks are for Exynos-M1.

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Comment at: llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll:3
@@ -2,1 +2,3 @@
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast -mcpu=exynos-m1 | FileCheck --check-prefix=EXYNOS %s
+; The instruction latencies of Exynos-M1 triggers the transform we see under the Exynos check.
 
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s/triggers/trigger/


https://reviews.llvm.org/D21571